公开(公告)号：US20220038079A1

公开(公告)日：2022-02-03

申请号：US17377087

申请日：2021-07-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kashyap Jayendra Barot ,  Suvadip Banerjee ,  Sreeram Subramanyam Nasum

IPC: H03K3/0233 ,  H02M1/00 ,  H02M1/14 ,  H02M1/08 ,  H02M3/335

Abstract: An apparatus includes a first control circuit having an output and including a first comparator and a second control circuit coupled to the output of the first control circuit. The second control circuit includes a second comparator configured to: compare a first value to a reference frequency value, the first value indicating a frequency of a signal at the output of the first control circuit; and provide an adjustment value to change a hysteresis window of the first comparator.

公开(公告)号：US11038461B2

公开(公告)日：2021-06-15

申请号：US16998526

申请日：2020-08-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Tarunvir Singh ,  Kumar Anurag Shrivastava ,  Somshubhra Paul ,  Sreeram Subramanyam Nasum

IPC: H03B5/12 ,  H03F3/45

Abstract: A digital isolator comprising a set of bipolar transistors and an inductor capacitor (LC) oscillator coupled to the set of bipolar transistors in series, wherein the LC oscillator is configured to be turned on and off based on the current applied to the set of bipolar transistors or the LC oscillator and generate a set of differential signals based on the current flowing through the set of bipolar transistors and mimicking the operational characteristics of an optocoupler.

公开(公告)号：US20220077788A1

公开(公告)日：2022-03-10

申请号：US17236931

申请日：2021-04-21

Applicant: Texas Instruments Incorporated

Inventor： Tarunvir Singh ,  Suvadip Banerjee ,  Sreeram Subramanyam Nasum

IPC: H02M3/335 ,  H02M1/088

Abstract: DC-DC power converter architecture is disclosed. In an example, an integrated circuit includes an H-bridge switching circuit operatively coupled with a transformer. The switching circuit is compensated to account for parasitic differences between the high-side (power) and low-side (ground). For instance, PMOS transistors connected to the high-side are sized larger to substantially match on-resistance of NMOS transistors connected to the low-side (e.g., such that the on-resistances are all within a tolerance of one another, or within a tolerance of a target on-resistance value), and the NMOS transistors include additional gate-drain capacitance to substantially match gate-drain capacitance of the larger PMOS transistors (e.g., such that the gate-drain capacitances are all within a tolerance of one another, or within a tolerance of a target gate-drain capacitance value). In addition, the transformer is configured with physical symmetry, such that the inductive and capacitive mid-points of the transformer are substantially co-located.

公开(公告)号：US11237581B2

公开(公告)日：2022-02-01

申请号：US16727586

申请日：2019-12-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Niranjan Shankar ,  Sreeram Subramanyam Nasum

IPC: G05F1/56

Abstract: A low-dropout voltage system comprising a current supply with a transistor circuitry, a mode switch capacitor, and a decoupling capacitor, wherein the mode switch capacitor facilitates the low-drop voltage system to swiftly transition from a low mode with a minimal to no transient current output to a high mode with a transient current of about 6 mA by dynamically biasing the transistor circuitry while limiting a voltage or current draw from an external power source.

公开(公告)号：US11205611B1

公开(公告)日：2021-12-21

申请号：US16901310

申请日：2020-06-15

Applicant: Texas Instruments Incorporated

Inventor： Vijaylaximi Khanolkar ,  Sreeram Subramanyam Nasum ,  Tarunvir Singh

IPC: H01L23/49 ,  H01L23/495 ,  H01L23/00 ,  H01L21/56 ,  H01L23/492

Abstract: An electronic device having a package structure with conductive leads, first and second dies in the package structure, as well as first and second conductive plates electrically coupled to the respective first and second dies and having respective first and second sides spaced apart from and directly facing one another with a portion of the package structure extending between the first side of the first conductive plate and the second side of the second conductive plate to form a capacitor. No other side of the first conductive plate directly faces a side of the second conductive plate, and no other side of the second conductive plate directly faces a side of the first conductive plate.

公开(公告)号：US20210391240A1

公开(公告)日：2021-12-16

申请号：US16901310

申请日：2020-06-15

Applicant: Texas Instruments Incorporated

Inventor： Vijaylaximi Khanolkar ,  Sreeram Subramanyam Nasum ,  Tarunvir Singh

IPC: H01L23/495 ,  H01L23/492 ,  H01L21/56 ,  H01L23/00

Abstract: An electronic device having a package structure with conductive leads, first and second dies in the package structure, as well as first and second conductive plates electrically coupled to the respective first and second dies and having respective first and second sides spaced apart from and directly facing one another with a portion of the package structure extending between the first side of the first conductive plate and the second side of the second conductive plate to form a capacitor. No other side of the first conductive plate directly faces a side of the second conductive plate, and no other side of the second conductive plate directly faces a side of the first conductive plate.

公开(公告)号：US20170201399A1

公开(公告)日：2017-07-13

申请号：US15354149

申请日：2016-11-17

Applicant: Texas Instruments Incorporated

Inventor： Sudhir Komarla Adinarayana ,  Sreenivasa S. Mallia ,  Sreeram Subramanyam Nasum

IPC: H04L27/04 ,  H04B1/69 ,  H04B1/04 ,  H04B1/40

Abstract: An isolator chip includes a transmitter circuit coupled to provide differential output signals to respective first terminals of a first and a second capacitor and a receiver circuit coupled to receive the differential output signals from respective second terminals of the first and second capacitors. The transmitter circuit includes a voltage-clamping circuit coupled to receive an input signal and to provide a clamped signal, an oscillator coupled to receive the clamped signal and to provide the differential output signals, and a common mode transient immunity (CMTI) circuit that couples respective first terminals of the first and second capacitors to a lower rail responsive to the clamped signal being low.

公开(公告)号：US20220148912A1

公开(公告)日：2022-05-12

申请号：US17583322

申请日：2022-01-25

Applicant: Texas Instruments Incorporated

Inventor： Scott Robert Summerfelt ,  Thomas Dyer Bonifield ,  Sreeram Subramanyam Nasum ,  Peter Smeys ,  Benjamin Stassen Cook

IPC: H01L21/762 ,  H01L49/02 ,  H01L27/12 ,  H01L23/544 ,  H01L23/00 ,  H01L21/78

Abstract: In described examples of an integrated circuit (IC) there is a substrate of semiconductor material having a first region with a first transistor formed therein and a second region with a second transistor formed therein. An isolation trench extends through the substrate and separates the first region of the substrate from the second region of the substrate. An interconnect region having layers of dielectric is disposed on a top surface of the substrate. A dielectric polymer is disposed in the isolation trench and in a layer over the backside surface of the substrate. An edge of the polymer layer is separated from the perimeter edge of the substrate by a space.

公开(公告)号：US20220077038A1

公开(公告)日：2022-03-10

申请号：US17527994

申请日：2021-11-16

Applicant: Texas Instruments Incorporated

Inventor： Vijaylaxmi Khanolkar ,  Sreeram Subramanyam Nasum ,  Tarunvir Singh

IPC: H01L23/495 ,  H01L21/56 ,  H01L23/492 ,  H01L23/00

Abstract: An electronic device having a package structure with conductive leads, first and second dies in the package structure, as well as first and second conductive plates electrically coupled to the respective first and second dies and having respective first and second sides spaced apart from and directly facing one another with a portion of the package structure extending between the first side of the first conductive plate and the second side of the second conductive plate to form a capacitor. No other side of the first conductive plate directly faces a side of the second conductive plate, and no other side of the second conductive plate directly faces a side of the first conductive plate.

公开(公告)号：US10957655B2

公开(公告)日：2021-03-23

申请号：US16291042

申请日：2019-03-04

Applicant: Texas Instruments Incorporated

Inventor： Sreeram Subramanyam Nasum ,  Kumar Anurag Shrivastava ,  Jeffrey Alan West

IPC: H01L23/552 ,  H01L23/544 ,  H01L23/00 ,  H01L27/01 ,  H01L49/02 ,  H01L21/70

Abstract: An IC includes a substrate including metal levels thereon including a top and bottom metal level with at least a transmit (Tx) circuit and receive (Rx) circuit each having ≥1 isolation capacitor and an inductor. A scribe seal around the IC includes a first portion around the Tx circuit and second portion around the Rx circuit, utilizing ≥2 of the metal levels including at least an outer metal stack. The Tx and Rx circuits are side-by-side along a direction that defines a length for the scribe seal. The outer metal stack includes a neck region between the scribe seal portions including a shorting structure including metal level(s) for shorting together the outer metal stack of the scribe seal portions. An optional routing pass-through isolated from the shorting structure includes other metal layers connecting through the neck region between node(s) within the first and second scribe seal portion.