公开(公告)号：US11249130B2

公开(公告)日：2022-02-15

申请号：US15859244

申请日：2017-12-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yuguo Wang ,  Steven Loveless ,  Tathagata Chatterjee ,  Jerry Doorenbos

IPC: G01R31/26

Abstract: A system comprises a noise generator circuit and a noise envelope detector circuit. The noise generator circuit comprises a first amplifier including a single transistor pair that is operable to generate 1/f noise, an output amplifier coupled to the first amplifier and configured to generate a 1/f noise signal as a function of the 1/f noise. The noise envelope detector circuit comprises a low pass filter operable to pass low frequency signals of the 1/f noise signal as a filtered 1/f noise signal, and a second amplifier or a comparator coupled to the low pass filter and operable to output a direct current (DC) voltage signal according to an envelope of the filtered 1/f noise signal, where the DC voltage signal is a function of an envelope of the filtered 1/f noise signal.

公开(公告)号：US20220082608A1

公开(公告)日：2022-03-17

申请号：US17537007

申请日：2021-11-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yuguo Wang ,  Steven Loveless ,  Tathagata Chatterjee ,  Jerry Doorenbos

IPC: G01R31/26

Abstract: A system comprises a noise generator circuit and a noise envelope detector circuit. The noise generator circuit comprises a first amplifier including a single transistor pair that is operable to generate 1/f noise, an output amplifier coupled to the first amplifier and configured to generate a 1/f noise signal as a function of the 1/f noise. The noise envelope detector circuit comprises a low pass filter operable to pass low frequency signals of the 1/f noise signal as a filtered 1/f noise signal, and a second amplifier or a comparator coupled to the low pass filter and operable to output a direct current (DC) voltage signal according to an envelope of the filtered 1/f noise signal, where the DC voltage signal is a function of an envelope of the filtered 1/f noise signal.

公开(公告)号：US11796588B2

公开(公告)日：2023-10-24

申请号：US17537007

申请日：2021-11-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yuguo Wang ,  Steven Loveless ,  Tathagata Chatterjee ,  Jerry Doorenbos

IPC: G01R31/26

CPC classification number: G01R31/2626

Abstract: A system comprises a noise generator circuit and a noise envelope detector circuit. The noise generator circuit comprises a first amplifier including a single transistor pair that is operable to generate 1/f noise, an output amplifier coupled to the first amplifier and configured to generate a 1/f noise signal as a function of the 1/f noise. The noise envelope detector circuit comprises a low pass filter operable to pass low frequency signals of the 1/f noise signal as a filtered 1/f noise signal, and a second amplifier or a comparator coupled to the low pass filter and operable to output a direct current (DC) voltage signal according to an envelope of the filtered 1/f noise signal, where the DC voltage signal is a function of an envelope of the filtered 1/f noise signal.

公开(公告)号：US10748818B2

公开(公告)日：2020-08-18

申请号：US16231243

申请日：2018-12-21

Applicant: Texas Instruments Incorporated

Inventor： Tathagata Chatterjee ,  Steven Loveless ,  James Robert Todd ,  Andrew Strachan

IPC: H01L49/02 ,  H01L21/8234 ,  H01L21/762 ,  H01L23/528 ,  H01L23/00 ,  H01L23/532

Abstract: In various examples, a method and apparatus are provided to achieve dynamic biasing to mitigate electrical stress. Described examples include a device includes a first resistor portion having a first terminal and a second terminal, and a second resistor portion having a third terminal and a fourth terminal. The device also includes a well in a substrate proximate to the first resistor portion and the second resistor portion and an insulating layer between the well and the first resistor portion and the second resistor portion. The device also includes a transistor having a control terminal coupled to the second terminal of the first resistor portion and the third terminal of the second resistor portion, the transistor having a first current-handling terminal coupled to a first voltage and a second current-handling terminal coupled to a current source and to the well.