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    EMBEDDED INDUCTOR MODULE AND PACKAGED SEMICONDUCTOR DEVICE
    4.
    发明申请
    EMBEDDED INDUCTOR MODULE AND PACKAGED SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20240429216A1

    公开(公告)日：2024-12-26

    申请号：US18650795

    申请日：2024-04-30

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Jie CHEN ,  Rajen MURUGAN ,  Sylvester ANKAMAH-KUSI ,  Harshpreet Singh Phull BAKSHI ,  Jonathan NOQUIL

    IPC: H01L25/16 ,  H01L21/48 ,  H01L23/00 ,  H01L23/13 ,  H01L23/498

    Abstract: An example method includes forming a cavity in a multi-layer substrate of a leadframe. The cavity extends from a first substrate surface of the leadframe into the multi-layer substrate to define a cavity floor spaced from the first substrate surface by a cavity sidewall, and at least one conductive terminal is on the cavity floor. The method also includes placing an inductor module in the cavity, in which the inductor module includes a conductor embedded within a dielectric substrate between spaced apart first and second inductor terminals of the inductor module. The method also includes coupling at least one of the first and second inductor terminals to the at least one conductive terminal on the cavity floor. The method also includes encapsulating the inductor module and at least a portion of the leadframe with a mold compound.

    BUILD-UP FILM AND PRE-PREG SUBSTRATES IN ISOLATION PACKAGES
    5.
    发明申请
    BUILD-UP FILM AND PRE-PREG SUBSTRATES IN ISOLATION PACKAGES 有权

    公开(公告)号：US20250167125A1

    公开(公告)日：2025-05-22

    申请号：US18920738

    申请日：2024-10-18

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Sylvester ANKAMAH-KUSI ,  Guangxu LI ,  Rajen Manicon MURUGAN ,  Usman CHAUDHRY

    IPC: H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L23/14 ,  H01L23/31 ,  H01L25/00 ,  H01L25/065

    Abstract: In examples, a semiconductor package includes a substrate including a build-up film isolation layer and first and second pre-preg layers contacting opposing lateral sides of the build-up film isolation layer, the first pre-preg layer including a first metallization, and the second pre-preg layer including a second metallization not in physical contact with the first metallization. The package also includes solder mask layers on top and bottom surfaces of the substrate, a first semiconductor die coupled to the first metallization, and a second semiconductor die coupled to the second metallization, the first and second semiconductor dies configured to operate in separate voltage domains. The package also includes a mold compound covering the substrate and the first and second semiconductor dies.

    WIDE BANDGAP POWER DEVICES WITH LOW POWER LOOP INDUCTANCE
    6.
    发明申请
    WIDE BANDGAP POWER DEVICES WITH LOW POWER LOOP INDUCTANCE 有权

    公开(公告)号：US20250112126A1

    公开(公告)日：2025-04-03

    申请号：US18478715

    申请日：2023-09-29

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Jie CHEN ,  Sylvester ANKAMAH-KUSI ,  Rajen Manicon MURUGAN ,  Yong XIE ,  Danny Lee BRIJA

    IPC: H01L23/495 ,  H01L23/00 ,  H01L25/065 ,  H01L29/16 ,  H01L29/20 ,  H01L29/778

    Abstract: In examples, a power device comprises a first wide bandgap semiconductor die including a high-side transistor; a second wide bandgap semiconductor die including a low-side transistor; and a conductive device coupled to the first and second wide bandgap semiconductor dies. The conductive device comprises a first layer including a first metal member having fingers at first and second ends of the first metal member, a second metal member having fingers interleaved with fingers of the first metal member at the first end, and a third metal member having fingers interleaved with fingers of the first metal member at the second end. The conductive device also comprises multiple layers in vertical alignment with the first layer, the first, second, and third metal members extending through the multiple layers. The conductive device also comprises a dielectric material covering the first layer and the multiple layers. The power device comprises a connection layer coupling the conductive device to each of the first and second wide bandgap semiconductor dies, with the connection layer including the first, second, and third metal members, and with the first metal member having connection layer fingers at the first and second ends of the first metal member. The second metal member has connection layer fingers interleaved with connection layer fingers of the first metal member at the first end, and the third metal member has connection layer fingers interleaved with connection layer fingers of the first metal member at the second end.

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