公开(公告)号：US09385044B2

公开(公告)日：2016-07-05

申请号：US14142144

申请日：2013-12-27

Applicant: Texas Instruments Incorporated

Inventor： Tom Lii

IPC: H01L21/336 ,  H01L21/28 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L21/3105 ,  H01L21/311

CPC classification number: H01L21/823437 ,  H01L21/28114 ,  H01L21/31053 ,  H01L21/31116 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/78

Abstract: An integrated circuit containing metal replacement gates may be formed by forming a CMP stop layer over sacrificial gates, and forming a dielectric fill layer over the CMP stop layer. Dielectric material from the dielectric fill layer is removed from over the sacrificial gates using a CMP process which exposes the CMP stop layer over the sacrificial gates but does not expose the sacrificial gates. The CMP stop layer is removed from over the sacrificial gates using a plasma etch process. In one version, the plasma etch process may be selective to the CMP stop layer. In another version, the plasma etch process may be a non-selective etch process. After the sacrificial gates are exposed by the plasma etch process, the sacrificial gates are removed and the metal replacement gates are formed.

Abstract translation: 可以通过在牺牲栅极上形成CMP停止层并在CMP停止层上形成介电填充层来形成包含金属替换栅极的集成电路。 使用CMP工艺从牺牲栅极上方去除介电填充层的电介质材料，CMP工艺使CMP停止层暴露在牺牲栅极上，但不暴露牺牲栅极。 使用等离子体蚀刻工艺从牺牲栅极上去除CMP停止层。 在一个版本中，等离子体蚀刻工艺可能对CMP停止层是选择性的。 在另一个版本中，等离子体蚀刻工艺可以是非选择性蚀刻工艺。 在通过等离子体蚀刻工艺暴露牺牲栅极之后，去除牺牲栅极并形成金属替换栅极。

公开(公告)号：US20140187009A1

公开(公告)日：2014-07-03

申请号：US14142075

申请日：2013-12-27

Applicant: Texas Instruments Incorporated

Inventor： Tom Lii ,  David Farber

IPC: H01L21/311 ,  H01L29/66

CPC classification number: H01L21/31116 ,  H01J37/32357 ,  H01L21/0217 ,  H01L21/31144 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/823864 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7843

Abstract: An integrated circuit may be formed by forming a sacrificial silicon nitride feature. At least a portion of the sacrificial silicon nitride feature may be removed by placing the integrated circuit in a two-step oxidized layer etch tool and removing a surface layer of oxidized silicon from the sacrificial silicon nitride feature using a two-step etch process. The two-step etch process exposes the integrated circuits to reactants from a plasma source at a temperature less than 40° C. and subsequently heating the integrated circuit to 80° C. to 120° C. while in the two-step oxidized layer etch tool. While the integrated circuit is in the two-step oxidized layer etch tool, without exposing the integrated circuit to an ambient containing more than 1 torr of oxygen, at least a portion of the sacrificial silicon nitride feature is removed using fluorine-containing etch reagents, substantially free of ammonia.

Abstract translation: 可以通过形成牺牲氮化硅特征来形成集成电路。 牺牲氮化硅特征的至少一部分可以通过将集成电路放置在两步氧化层蚀刻工具中并且使用两步蚀刻工艺从牺牲氮化硅特征中除去氧化硅的表面层来去除。 两步蚀刻工艺将集成电路暴露于等离子体源的温度低于40℃的反应物，随后将集成电路加热至80℃至120℃，同时在两步氧化层蚀刻 工具。 当集成电路处于两步氧化层蚀刻工具中时，不将集成电路暴露于含有超过1托的氧的环境中，使用含氟蚀刻剂除去至少一部分牺牲氮化硅特征， 基本上不含氨。

公开(公告)号：US09704720B2

公开(公告)日：2017-07-11

申请号：US15228204

申请日：2016-08-04

Applicant: Texas Instruments Incorporated

Inventor： Tom Lii ,  David Farber

IPC: H01L21/311 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01J37/32 ,  H01L21/02

CPC classification number: H01L21/31116 ,  H01J37/32357 ,  H01L21/0217 ,  H01L21/31144 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/823864 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7843

Abstract: An integrated circuit may be formed by forming a sacrificial silicon nitride feature. At least a portion of the sacrificial silicon nitride feature may be removed by placing the integrated circuit in a two-step oxidized layer etch tool and removing a surface layer of oxidized silicon from the sacrificial silicon nitride feature using a two-step etch process. The two-step etch process exposes the integrated circuits to reactants from a plasma source at a temperature less than 40° C. and subsequently heating the integrated circuit to 80° C. to 120° C. while in the two-step oxidized layer etch tool. While the integrated circuit is in the two-step oxidized layer etch tool, without exposing the integrated circuit to an ambient containing more than 1 torr of oxygen, at least a portion of the sacrificial silicon nitride feature is removed using fluorine-containing etch reagents, substantially free of ammonia.

公开(公告)号：US20160307808A1

公开(公告)日：2016-10-20

申请号：US15193270

申请日：2016-06-27

Applicant: Texas Instruments Incorporated

Inventor： Tom Lii

IPC: H01L21/8238

CPC classification number: H01L21/823864 ,  H01L21/31 ,  H01L21/31105 ,  H01L21/31111 ,  H01L21/823425 ,  H01L21/8238 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823835 ,  H01L21/823857 ,  H01L27/092 ,  H01L29/42364 ,  H01L29/512 ,  H01L29/518 ,  H01L29/6656

Abstract: An integrated circuit may be formed by removing source/drain spacers from offset spacers on sidewalls of MOS transistor gates, forming a contact etch stop layer (CESL) spacer layer on lateral surfaces of the MOS transistor gates, etching back the CESL spacer layer to form sloped CESL spacers on the lateral surfaces of the MOS transistor gates with heights of ¼ to ¾ of the MOS transistor gates, forming a CESL over the sloped CESL spacers, the MOS transistor gates and the intervening substrate, and forming a PMD layer over the CESL.

公开(公告)号：US09054158B2

公开(公告)日：2015-06-09

申请号：US13762529

申请日：2013-02-08

Applicant: Texas Instruments Incorporated

Inventor： David Gerald Farber ,  Tom Lii ,  Steve Lytle

IPC: H01L21/00 ,  H01L21/768

CPC classification number: H01L21/76804 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76897

Abstract: The width of a metal contact opening is formed to be smaller than the minimum feature size of a photolithographically-defined opening. The method forms the metal contact opening by first etching the fourth layer of a multilayered hard mask structure to have a number of trenches that expose the third layer of the multilayered hard mask structure. Following this, the third, second, and first layers of the multilayered hard mask structure are selectively etched to expose uncovered regions on the top surface of an isolation layer that touches and lies over a source region and a drain region. The uncovered regions on the top surface of the isolation layer are then etched to form the metal contact openings.

Abstract translation: 金属接触开口的宽度形成为小于光刻限定开口的最小特征尺寸。 该方法通过首先蚀刻多层硬掩模结构的第四层来形成金属接触开口，以具有暴露多层硬掩模结构的第三层的多个沟槽。 接下来，选择性地蚀刻多层硬掩模结构的第三层，第二层和第一层，以暴露接触并位于源极区域和漏极区域上的隔离层的顶表面上的未覆盖区域。 然后蚀刻隔离层的顶表面上的未覆盖区域以形成金属接触开口。

公开(公告)号：US10134731B2

公开(公告)日：2018-11-20

申请号：US15490466

申请日：2017-04-18

Applicant: Texas Instruments Incorporated

Inventor： Tom Lii

IPC: H01L27/092 ,  H01L21/285 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51

Abstract: A method for forming MOS transistor includes providing a substrate including a semiconductor surface having a gate electrode on a gate dielectric thereon, dielectric spacers on sidewalls of the gate electrode, a source and drain in the semiconductor surface on opposing sides of the gate electrode, and a pre-metal dielectric (PMD) layer over the gate electrode and over the source and drain regions. Contact holes are formed through the PMD layer to form a contact to the gate electrode and contacts to the source and drain. A post contact etch dielectric layer is then deposited on the contacts to source and drain and on sidewalls of the PMD layer. The post contact etch dielectric layer is selectively removed from the contacts to leave a dielectric liner on sidewalls of the PMD layer. A metal silicide layer is formed on the contacts to the source and drain.

公开(公告)号：US20160343581A1

公开(公告)日：2016-11-24

申请号：US15228204

申请日：2016-08-04

Applicant: Texas Instruments Incorporated

Inventor： Tom Lii ,  David Farber

IPC: H01L21/311 ,  H01L21/02 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L21/31116 ,  H01J37/32357 ,  H01L21/0217 ,  H01L21/31144 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/823864 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7843

Abstract: An integrated circuit may be formed by forming a sacrificial silicon nitride feature. At least a portion of the sacrificial silicon nitride feature may be removed by placing the integrated circuit in a two-step oxidized layer etch tool and removing a surface layer of oxidized silicon from the sacrificial silicon nitride feature using a two-step etch process. The two-step etch process exposes the integrated circuits to reactants from a plasma source at a temperature less than 40° C. and subsequently heating the integrated circuit to 80° C. to 120° C. while in the two-step oxidized layer etch tool. While the integrated circuit is in the two-step oxidized layer etch tool, without exposing the integrated circuit to an ambient containing more than 1 torr of oxygen, at least a portion of the sacrificial silicon nitride feature is removed using fluorine-containing etch reagents, substantially free of ammonia.

Abstract translation: 可以通过形成牺牲氮化硅特征来形成集成电路。 牺牲氮化硅特征的至少一部分可以通过将集成电路放置在两步氧化层蚀刻工具中并且使用两步蚀刻工艺从牺牲氮化硅特征中去除氧化硅的表面层来去除。 两步蚀刻工艺将集成电路暴露于等离子体源的温度低于40℃的反应物，随后将集成电路加热至80℃至120℃，同时在两步氧化层蚀刻 工具。 当集成电路处于两步氧化层蚀刻工具中时，不将集成电路暴露于含有超过1托的氧的环境中，使用含氟蚀刻剂除去至少一部分牺牲氮化硅特征， 基本上不含氨。

公开(公告)号：US09406779B2

公开(公告)日：2016-08-02

申请号：US14746009

申请日：2015-06-22

Applicant: Texas Instruments Incorporated

Inventor： Tom Lii

IPC: H01L21/8238 ,  H01L29/66 ,  H01L27/092 ,  H01L21/8234 ,  H01L21/31 ,  H01L21/311 ,  H01L29/423 ,  H01L29/51

CPC classification number: H01L21/823864 ,  H01L21/31 ,  H01L21/31105 ,  H01L21/31111 ,  H01L21/823425 ,  H01L21/8238 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823835 ,  H01L21/823857 ,  H01L27/092 ,  H01L29/42364 ,  H01L29/512 ,  H01L29/518 ,  H01L29/6656

Abstract: An integrated circuit may be formed by removing source/drain spacers from offset spacers on sidewalls of MOS transistor gates, forming a contact etch stop layer (CESL) spacer layer on lateral surfaces of the MOS transistor gates, etching back the CESL spacer layer to form sloped CESL spacers on the lateral surfaces of the MOS transistor gates with heights of ¼ to ¾ of the MOS transistor gates, forming a CESL over the sloped CESL spacers, the MOS transistor gates and the intervening substrate, and forming a PMD layer over the CESL.

公开(公告)号：US20150287804A1

公开(公告)日：2015-10-08

申请号：US14746009

申请日：2015-06-22

Applicant: Texas Instruments Incorporated

Inventor： Tom Lii

IPC: H01L29/66 ,  H01L21/31 ,  H01L29/51 ,  H01L29/423 ,  H01L21/8238 ,  H01L21/311

CPC classification number: H01L21/823864 ,  H01L21/31 ,  H01L21/31105 ,  H01L21/31111 ,  H01L21/823425 ,  H01L21/8238 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823835 ,  H01L21/823857 ,  H01L27/092 ,  H01L29/42364 ,  H01L29/512 ,  H01L29/518 ,  H01L29/6656

Abstract: An integrated circuit may be formed by removing source/drain spacers from offset spacers on sidewalls of MOS transistor gates, forming a contact etch stop layer (CESL) spacer layer on lateral surfaces of the MOS transistor gates, etching back the CESL spacer layer to form sloped CESL spacers on the lateral surfaces of the MOS transistor gates with heights of ¼ to ¾ of the MOS transistor gates, forming a CESL over the sloped CESL spacers, the MOS transistor gates and the intervening substrate, and forming a PMD layer over the CESL.

Abstract translation: 可以通过从MOS晶体管栅极的侧壁上的偏移间隔物去除源/漏间隔物来形成集成电路，在MOS晶体管栅极的侧表面上形成接触蚀刻停止层（CESL）间隔层，蚀刻CESL间隔层以形成 在MOS晶体管栅极的横向表面上倾斜的CESL间隔物，其高度为MOS晶体管栅极的1/4至¾，在倾斜的CESL间隔物，MOS晶体管栅极和介入衬底上形成CESL，并在CESL上形成PMD层 。

公开(公告)号：US20150187661A1

公开(公告)日：2015-07-02

申请号：US14575512

申请日：2014-12-18

Applicant: Texas Instruments Incorporated

Inventor： Tom Lii ,  David Farber

IPC: H01L21/8238 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/311

CPC classification number: H01L21/823864 ,  H01L21/823814

Abstract: A process for forming an integrated circuit with an embedded epitaxially grown semiconductor using an epi blocking bilayer. The epi blocking bilayer comprised of a two different materials that may be etched selectively with respect to each other such as silicon nitride and silicon dioxide.

Abstract translation: 使用外延阻挡双层形成具有嵌入式外延生长半导体的集成电路的工艺。 外延阻挡双层由可相对于彼此选择性地蚀刻的两种不同材料组成，例如氮化硅和二氧化硅。