公开(公告)号：US09411007B2

公开(公告)日：2016-08-09

申请号：US13663258

申请日：2012-10-29

申请人： THE REGENTS OF THE UNIVERSITY OF MICHIGAN

发明人： Valeria Bertacco ,  Andrew DeOrio ,  Daya Shanker Khudia

IPC分类号： G01R31/26 ,  G01R29/26 ,  G01R27/28 ,  G06F11/263 ,  G01R31/3183 ,  G06F11/26 ,  G01R31/3185

CPC分类号： G01R31/2601 ,  G01R27/28 ,  G01R29/26 ,  G01R31/31705 ,  G01R31/31707 ,  G01R31/3183 ,  G01R31/318544 ,  G06F11/261 ,  G06F11/263

摘要： The system and method described herein relate to a bug positioning system for post-silicon validation of a prototype integrated circuit using statistical analysis. Specifically, the bug positioning system samples output and intermediate signals from a prototype chip to generate signatures. Signatures are grouped into passing and failing groups, modeled, and compared to identify patterns of acceptable behavior and unacceptable behavior and locate bugs in space and time.

摘要翻译： 本文描述的系统和方法涉及使用统计分析的原型集成电路的硅后验证的错误定位系统。 具体来说，错误定位系统从原型芯片采样输出和中间信号以产生签名。 签名被分组为通过和失败的组，建模和比较，以识别可接受的行为和不可接受的行为的模式，并定位空间和时间的错误。

公开(公告)号：US11232212B2

公开(公告)日：2022-01-25

申请号：US16546850

申请日：2019-08-21

申请人： THE REGENTS OF THE UNIVERSITY OF MICHIGAN

发明人： Todd Austin ,  Valeria Bertacco ,  Mark Gallagher ,  Baris Kasikci

IPC分类号： G06F21/57 ,  G06F8/65 ,  G06F21/55 ,  G06F21/56 ,  G06F21/60 ,  H04L9/08

摘要： A computer system includes an ensemble moving target defense architecture that protects the computer system against attack using a plurality of composable protection layers that change each churn cycle, thereby requiring an attacker to acquire information needed for an attack (e.g., code and pointers) and successfully deploy the attack, before the layers have changed state. Each layer may deploy a different attack information asset protection providing multiple different attack protections each churn cycle.

公开(公告)号：US11868283B2

公开(公告)日：2024-01-09

申请号：US16932183

申请日：2020-07-17

申请人： THE REGENTS OF THE UNIVERSITY OF MICHIGAN

发明人： Valeria Bertacco ,  Abraham Addisie

IPC分类号： G06F13/16 ,  G06F13/42 ,  G06F13/40 ,  G06F16/955 ,  G06F16/901 ,  G06F3/06

CPC分类号： G06F13/1668 ,  G06F3/0655 ,  G06F13/4027 ,  G06F13/4282 ,  G06F16/9024 ,  G06F16/9558

摘要： The increased use of graph algorithms in diverse fields has highlighted their inefficiencies in current chip-multiprocessor (CMP) architectures, primarily due to their seemingly random-access patterns to off-chip memory. Here, a novel computer memory architecture is proposed that processes operations on vertex data in on-chip memory and off-chip memory. The hybrid computer memory architecture utilizes a vertex's degree as a proxy to determine whether to process related operations in on-memory or off-chip memory. The proposed computer memory architecture manages to provide up to 4.0× improvement in performance and 3.8× in energy benefits, compared to a baseline CMP, and up to a 2.0× performance boost over state-of-the-art specialized solutions.