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公开(公告)号：US20200314293A1
公开(公告)日：2020-10-01
申请号：US16829491
申请日：2020-03-25
发明人： Tomohiro SAKAI , Kazuhisa SASAKI , Satoshi MIURA , Daisuke IWAMA
IPC分类号： H04N5/14 , G06F3/14 , H04N21/41 , H04N21/434
摘要： This embodiment relates to a transmitter and the like that prevent an increase of the number of cables of an external interface even when the types of signals to be transmitted increase. The transmitter includes a latch circuit, an encoder, a serializer, and a selector. The latch circuit keeps a level of each of a plurality of signals at the timing specified by a sampling clock, and then, outputs the plurality of signals as a parallel data signal. The encoder generates an encoded parallel data signal based on the parallel data signal from the latch circuit. The serializer generates a serial data signal based on the encoded parallel data signal from the encoder. The sampling clock has a frequency higher than a transmission rate of the fastest signal of the plurality of signals.
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公开(公告)号：US20190363704A1
公开(公告)日：2019-11-28
申请号：US16420564
申请日：2019-05-23
发明人： Satoshi MIURA , Yusuke FUJITA
摘要： A duty compensation device of one embodiment has a structure capable of more accurately setting a duty of a clock within an appropriate range. The duty compensation device comprises a duty adjusting unit, a duty measuring unit, a controlling unit. The duty measuring unit generates a sampling clock of a frequency fn that is asynchronous to the clock over an n-th period Tn (n=1 to N and N is an integer of 3 or more), and obtains measurement information for specifying the duty of the clock by using the sampling clock. The controlling unit determines a control code to be given to the duty adjusting unit based on control code candidates obtained for each of the N periods T1 to TN and the control code candidates in which the duty specified by measurement information obtained by the duty measuring unit is within a predetermined range.
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公开(公告)号：US20180062701A1
公开(公告)日：2018-03-01
申请号：US15555287
申请日：2016-02-18
发明人： Satoshi MIURA
CPC分类号： H04B3/50 , H04B3/02 , H04L25/02 , H04L25/0264 , H04L25/03019
摘要： The invention relates to a reception device, etc., applied to a transmission/reception system capable of performing high-speed transmission, having a structure to enable to adjust an offset without increasing a circuit area and power consumption. The reception device includes a signal input unit including an offset adjusting circuit, and an adjustment unit. When a pair of adjusting signals of which a voltage between signals is fixed to zero V is outputted from a transmission device to the reception device connected to each other via a differential signal line including at least a pair of signal lines, the signal input unit that has received the pair of adjusting signals outputs logical value data corresponding to the voltage between signals. The adjustment unit determines adjustment value data to adjust the offset of a threshold to obtain the logical value data based on the logical value data inputted in a certain period.
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公开(公告)号：US20190273501A1
公开(公告)日：2019-09-05
申请号：US16291604
申请日：2019-03-04
摘要： A PLL circuit includes a phase comparator, a charge pump 20, a loop filter 30, a voltage controlled oscillator 40, a frequency divider, and a phase compensator 70. The loop filter 30 includes a resistor 31, a first capacitance element 32, and a second capacitance element 33. The phase compensator 70 is provided in parallel to the charge pump 20 and adds a differentiation term to an open-loop transfer function. The phase compensator 70 includes a buffer 71 receiving a phase difference signal output from the phase comparator and a third capacitance element 72 provided between an output terminal of the buffer 71 and an input terminal of the loop filter 30.
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公开(公告)号：US20210234553A1
公开(公告)日：2021-07-29
申请号：US16972349
申请日：2019-06-19
发明人： Satoshi MIURA , Yusuke FUJITA
摘要： A multi-lane serializer device 1 includes serializer circuits 101 to 10N and a controller 20. A phase difference detector of each serializer circuit detects a phase difference between a load signal and a first clock, and outputs an abnormal detection signal to the controller 20 when the detected phase difference is abnormal. When the controller 20 receives the abnormal detection signal from any of the serializer circuits, the controller 20 transmits a batch reset instruction signal to all the serializer circuits. Then, in all the serializer circuits, when a reset signal generator receives the batch reset instruction signal output from the controller 20, the reset signal generator transmits a reset instruction signal to a load signal generator to reset the operation of a load signal generation in the load signal generator.
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公开(公告)号：US20210058078A1
公开(公告)日：2021-02-25
申请号：US16997076
申请日：2020-08-19
IPC分类号： H03K5/1252 , H03F3/193 , H04B1/04
摘要： An XTC circuit includes delay circuits, differentiated signal generating circuits, and an amplitude adjusting and adding circuit. A signal Da, which is one aggressor signal, is input to the differentiated signal generating circuit after being delayed by the delay circuit, and the differentiated signal generating circuit generates a differentiated signal having a differentiated waveform of the signal Da. In the amplitude adjusting and adding circuit, the differentiated signal generated by the differentiated signal generating circuit is amplitude-adjusted to become a current signal, and the differentiated signal after the amplitude adjustment is current-added to the signal Db.
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7.发明申请公开(公告)号：US20190158798A1
公开(公告)日：2019-05-23
申请号：US16091230
申请日：2017-04-06
摘要： The present invention relates to a video signal transmission device and the like that can support a variety of system specifications. The device includes a packer unit, an encoder unit, and a serializer. The packer unit generates, from a video signal of one or more pixels, a plurality of block signals having a packet configuration of size corresponding to the number of pixels and the number of tone bits of a color signal constituting a video signal. At this time, a control signal including a pulse having a width corresponding to the number of pixels and the number of tone bits is also generated. The encoder unit applies encoding processing having encoding efficiencies that are different between a first period and a second period of a control signal that are distinguished depending on existence or non-existence of a pulse to the block signals.
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公开(公告)号：US20170338813A1
公开(公告)日：2017-11-23
申请号：US15596200
申请日：2017-05-16
发明人： Yusuke FUJITA , Satoshi MIURA
IPC分类号： H03K17/284 , H03K19/20 , H03K17/693
CPC分类号： H03K17/284 , H03K17/693 , H03K19/20
摘要： A signal multiplexer according to the present embodiment has a configuration sufficiently capable of accelerating a data rate. The signal multiplexer includes M number of front units and a rear unit. An m-th front unit Am outputs an output signal corresponding to an m-th input signal Im when both the control signal Cm and the control signal Cn are significant levels, and outputs an output signal having a fixed level when at least either one of the control signal Cm or the control signal Cn is an non-significant level. A rear unit B receives signals from the front units, and outputs a signal having a different signal level in a case in which all the output signals from the front units are the same level or in the other case.
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公开(公告)号：US20170118010A1
公开(公告)日：2017-04-27
申请号：US15302068
申请日：2015-03-11
发明人： Yusuke FUJITA , Satoshi MIURA , Shunichi KUBO
CPC分类号： H04L7/0083 , H03L7/0807 , H04L7/0066 , H04L7/033 , H04L7/0331
摘要： A receiving device 20 includes a voltage controlled oscillator 22, a sampling unit 23, a control voltage generating unit 24, an error detecting unit 25, and a control voltage holding unit 26. The control voltage holding unit 26 holds a value of a control voltage Vc output from the control voltage generating unit 24. When the error detecting unit 25 detects an error of a digital signal, a control voltage held before error detection is provided to the voltage controlled oscillator 22.
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公开(公告)号：US20150333869A1
公开(公告)日：2015-11-19
申请号：US14712298
申请日：2015-05-14
发明人： Satoshi MIURA
CPC分类号： H04L25/0292 , G06F11/0706 , G06F11/0751 , H04L1/0045 , H04L25/0272
摘要： A receiving device includes a termination circuit to which a received signal is input, a processing circuit which performs a process at a rear stage of the termination circuit, and an error detection circuit which detects an error contained in the received signal. In a case where the error is detected by the error detection circuit, a termination resistance value of the termination circuit is lowered. Therefore, the receiving device can be rapidly restored when a signal containing an error is received.
摘要翻译： 接收装置包括输入接收信号的终端电路，执行终端电路的后级处理的处理电路和检测接收信号中包含的错误的错误检测电路。 在由错误检测电路检测出错误的情况下，终端电路的终端电阻值降低。 因此，当接收到包含错误的信号时，可以快速恢复接收装置。
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