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公开(公告)号：US20170221968A1
公开(公告)日：2017-08-03
申请号：US15487529
申请日：2017-04-14
Applicant: TOPPAN PRINTING CO., LTD.
Inventor： Ryohei MATSUBARA , Mamoru ISHIZAKI , Makoto NISHIZAWA
CPC classification number: H01L27/283 , G02F1/1368 , H01L27/285 , H01L29/786 , H01L51/0004 , H01L51/0558 , H01L51/107
Abstract: A thin-film transistor array includes a substrate and thin-film transistors positioned in matrix on the substrate. The thin-film transistors each include source and drain electrodes formed on a gate insulation layer, and a semiconductor layer formed on the gate insulation layer and positioned between the source and drain electrodes. The semiconductor layer is formed in stripes over the plurality of thin-film transistors such that one of the stripes has a long axis direction coinciding with a channel width direction of one of the thin-film transistors. The semiconductor layer has a cross section in a short axis direction of the stripe such that a thickness of the semiconductor layer gradually decreases outwardly from a center portion of the stripe.
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公开(公告)号：US20160211474A1
公开(公告)日：2016-07-21
申请号：US15082078
申请日：2016-03-28
Applicant: TOPPAN PRINTING CO., LTD.
Inventor： Ryohei MATSUBARA
CPC classification number: H01L51/0545 , G02F1/136227 , H01L27/1288 , H01L27/1292 , H01L27/3258 , H01L51/105 , H01L2227/323
Abstract: A thin film transistor array includes thin film transistors positioned in a matrix, each of the thin film transistors including a substrate, a gate electrode formed on the substrate, a gate insulation layer formed on the gate electrode, a source electrode formed on the gate insulation layer, a drain electrode formed on the gate insulation layer, a pixel electrode formed on the gate insulation layer and connected to the source electrode and the drain electrode, a semiconductor layer formed between the source electrode and the drain electrode, an interlayer insulation film covering the source electrode, the drain electrode, the semiconductor layer and a portion of the pixel electrode, and an upper pixel electrode formed on the interlayer insulation film and connected to the pixel electrode. The interlayer insulation film has one or more concave portions and one or more via hole portions.
Abstract translation: 薄膜晶体管阵列包括位于矩阵中的薄膜晶体管，每个薄膜晶体管包括基板，形成在基板上的栅电极，形成在栅电极上的栅极绝缘层，形成在栅绝缘层上的源电极 形成在栅绝缘层上的漏电极，形成在栅极绝缘层上并连接到源电极和漏电极的像素电极，形成在源电极和漏电极之间的半导体层，层间绝缘膜覆盖层 源电极，漏电极，半导体层和像素电极的一部分，以及形成在层间绝缘膜上并连接到像素电极的上像素电极。 层间绝缘膜具有一个或多个凹部和一个以上通孔部。
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公开(公告)号：US20150236083A1
公开(公告)日：2015-08-20
申请号：US14701145
申请日：2015-04-30
Applicant: TOPPAN PRINTING CO., LTD.
Inventor： Ryohei MATSUBARA
CPC classification number: H01L27/3274 , H01L27/283 , H01L27/3248 , H01L27/3262 , H01L27/3265 , H01L27/3276 , H01L28/40 , H01L51/0005 , H01L51/0022 , H01L51/0094 , H01L51/0096 , H01L51/0097 , H01L51/0545 , H01L51/0558
Abstract: A thin film transistor array includes thin film transistors each including a gate electrode formed on an insulation substrate, a source electrode and a drain electrode formed on the gate electrode via a gate insulation film and a semiconductor layer formed on a portion of the gate electrode surrounded by at least the source electrode and the drain electrode; capacitors each including a capacitor electrode formed on the insulation substrate and a pixel electrode which is formed on the capacitor electrode via the gate insulation film and connected to the drain electrode, the capacitors and the thin film transistors being positioned in a matrix along a first direction and a second direction perpendicular to the first direction; and connection lines that connect semiconductor layers of the thin film transistors positioned in the first direction. The connection lines each have a width smaller than a width of the semiconductor layer.
Abstract translation: 薄膜晶体管阵列包括薄膜晶体管，每个薄膜晶体管包括形成在绝缘基板上的栅极电极，通过栅极绝缘膜形成在栅电极上的源电极和漏电极，以及形成在栅电极的一部分上的半导体层 至少源极电极和漏电极; 每个包括形成在绝缘基板上的电容器电极的电容器和通过栅极绝缘膜形成在电容器电极上并连接到漏电极的像素电极，电容器和薄膜晶体管沿着第一方向位于矩阵中 和与第一方向垂直的第二方向; 以及连接线，其连接位于第一方向的薄膜晶体管的半导体层。 连接线各自具有比半导体层的宽度小的宽度。
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