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公开(公告)号:US20190287979A1
公开(公告)日:2019-09-19
申请号:US16122541
申请日:2018-09-05
Applicant: TOSHIBA MEMORY CORPORATION
Inventor: Kana HIRAYAMA , Kazuhiko YAMAMOTO , Kunifumi SUZUKI
Abstract: A nonvolatile semiconductor memory device includes a first wiring layer, multiple second wiring layers provided above the first wiring layer and arrayed along a direction perpendicular to a semiconductor substrate, a semiconductor layer extending along the direct ion and electrically connected to the first wiring layer, a first insulating layer extending along the direction and provided between the semiconductor layer and the multiple second wiring layers, a first oxide layer extending along the direction and provided between the first insulating layer and the multiple second wiring layers, and multiple second oxide layers having first sides being respectively in contact with the multiple second wiring layers and having second sides being in contact with the first oxide layer, a resistance value of a stacked film configured with the first oxide layer and the multiple second oxide layers varying according to a voltage being applied to the multiple second wiring layers.
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公开(公告)号:US20200083295A1
公开(公告)日:2020-03-12
申请号:US16279971
申请日:2019-02-19
Applicant: Toshiba Memory Corporation
Inventor: Yosuke MURAKAMI , Takeshi ISHIZAKI , Yusuke ARAYASHIKI , Kazuhiko YAMAMOTO , Kana HIRAYAMA
Abstract: A storage device includes a first conductor, a resistance variable film, and a second conductor. The resistance variable film includes a first layer and a second layer. The second layer is located on a side opposite to the first conductor with respect to the first layer, contains oxygen, and has conductivity higher than that of the first layer. The second conductor includes a first portion and a second portion. The first portion abuts on the second layer of the resistance variable film. The second portion is separated from the resistance variable film as compared to the first portion. The oxygen content of the first portion is higher than that of the second portion.
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公开(公告)号:US20180261651A1
公开(公告)日:2018-09-13
申请号:US15697388
申请日:2017-09-06
Applicant: TOSHIBA MEMORY CORPORATION
Inventor: Kana HIRAYAMA , Kazuhiko YAMAMOTO , Yusuke ARAYASHIKI , Yosuke MURAKAMI , Yusuke KOBAYASHI
CPC classification number: H01L27/249 , G11C13/0007 , G11C13/0069 , G11C13/0097 , G11C2213/32 , G11C2213/51 , G11C2213/52 , G11C2213/71 , H01L27/2436 , H01L45/08 , H01L45/1226 , H01L45/1246 , H01L45/1253 , H01L45/146
Abstract: According to one or more embodiments, a memory device includes a first interconnection extending in a first direction, a plurality of second interconnections extending in a second direction intersecting the first direction, and a first resistance change film provided between the first interconnection and the second interconnections. The first resistance change film includes a first conductive layer having a first conductivity, and a second conductive layer provided between the first conductive layer and the plurality of second interconnections and having a second conductivity higher than the first conductivity.
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