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    STORAGE DEVICE
    1.
    发明申请
    STORAGE DEVICE 审中-公开

    公开(公告)号：US20200098829A1

    公开(公告)日：2020-03-26

    申请号：US16289651

    申请日：2019-02-28

    Applicant: TOSHIBA MEMORY CORPORATION

    Inventor： Yusuke ARAYASHIKI ,  Nobuyuki MOMO ,  Motohiko FUJIMATSU ,  Akira HOKAZONO

    IPC: H01L27/24

    Abstract: A storage device includes: a substrate; a first conductive layer extending in a first direction; a second conductive layer adjacent to the first conductive layer in a second direction, and extending in the first direction; a third conductive layer extending in a third direction; a fourth conductive layer extending in the second direction; a fifth conductive layer disposed on the second conductive layer, extending in the third direction, and being electrically connected to the fourth conductive layer; a first storage layer disposed between the third conductive layer and the fourth conductive layer; a first semiconductor layer disposed between the first conductive layer and the third conductive layer; a second semiconductor layer disposed between the second conductive layer and the fifth conductive layer; and a first gate electrode extending in the second direction and being shared by side surfaces of the first semiconductor layer and the second semiconductor layer.

    MEMORY DEVICE
    2.
    发明申请
    MEMORY DEVICE 审中-公开

    公开(公告)号：US20190088715A1

    公开(公告)日：2019-03-21

    申请号：US15909454

    申请日：2018-03-01

    Applicant: TOSHIBA MEMORY CORPORATION

    Inventor： Kazuhiko YAMAMOTO ,  Yusuke ARAYASHIKI ,  Kana ISHIKAWA

    IPC: H01L27/24 ,  H01L45/00 ,  G11C13/00

    Abstract: A memory device includes a first conductive layer, a second conductive layer, and a variable resistance layer disposed between the first and second conductive layers. The variable resistance layer includes a first layer containing a semiconductor or a first metal oxide, a second layer disposed between the first layer and the first conductive layer, and containing a second metal oxide, and a first amorphous layer disposed between the second layer and the first conductive layer.

    STORAGE DEVICE
    3.
    发明申请
    STORAGE DEVICE 审中-公开

    公开(公告)号：US20200083295A1

    公开(公告)日：2020-03-12

    申请号：US16279971

    申请日：2019-02-19

    Applicant: Toshiba Memory Corporation

    Inventor： Yosuke MURAKAMI ,  Takeshi ISHIZAKI ,  Yusuke ARAYASHIKI ,  Kazuhiko YAMAMOTO ,  Kana HIRAYAMA

    IPC: H01L27/24 ,  H01L45/00

    Abstract: A storage device includes a first conductor, a resistance variable film, and a second conductor. The resistance variable film includes a first layer and a second layer. The second layer is located on a side opposite to the first conductor with respect to the first layer, contains oxygen, and has conductivity higher than that of the first layer. The second conductor includes a first portion and a second portion. The first portion abuts on the second layer of the resistance variable film. The second portion is separated from the resistance variable film as compared to the first portion. The oxygen content of the first portion is higher than that of the second portion.

    RESISTIVE RANDOM ACCESS MEMORY DEVICE WITH THREE-DIMENSIONAL CROSS-POINT STRUCTURE AND METHOD OF OPERATING THE SAME
    5.
    发明申请
    RESISTIVE RANDOM ACCESS MEMORY DEVICE WITH THREE-DIMENSIONAL CROSS-POINT STRUCTURE AND METHOD OF OPERATING THE SAME 有权

    公开(公告)号：US20210264976A1

    公开(公告)日：2021-08-26

    申请号：US17195994

    申请日：2021-03-09

    Applicant: TOSHIBA MEMORY CORPORATION

    Inventor： Kikuko SUGIMAE ,  Yusuke ARAYASHIKI

    IPC: G11C13/00 ,  H01L45/00 ,  H01L27/24

    Abstract: A memory device according to an embodiment includes a first interconnect, a second interconnect, a first variable resistance member, a third interconnect, a second variable resistance member, a fourth interconnect, a fifth interconnect and a third variable resistance member. The first interconnect, the third interconnect and the fourth interconnect extend in a first direction. The second interconnect and the fifth interconnect extend in a second direction crossing the first direction. The first variable resistance member is connected between the first interconnect and the second interconnect. The second variable resistance member is connected between the second interconnect and the third interconnect. The third variable resistance member is connected between the fourth interconnect and the fifth interconnect. The fourth interconnect is insulated from the third interconnect.

    SEMICONDUCTOR MEMORY DEVICE
    6.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20190296079A1

    公开(公告)日：2019-09-26

    申请号：US16129249

    申请日：2018-09-12

    Applicant: TOSHIBA MEMORY CORPORATION

    Inventor： Yosuke MURAKAMI ,  Yusuke ARAYASHIKI ,  Kazuhiko YAMAMOTO

    IPC: H01L27/24

    Abstract: According to one embodiment, a semiconductor memory device includes a substrate, a first signal line, a first conductive layer, a first storage layer and a first insulation layer. The first signal line extends in a first direction crossing the substrate. The first conductive layer extends in a second direction crossing the first direction and being parallel to the substrate, and has a first surface and a second surface that is away from the first signal line in a third direction crossing the first and second directions. The first storage layer is provided between the first signal line and the first conductive layer. The first insulation layer is provided between the second surface and the first storage layer.

    STORAGE DEVICE
    7.
    发明申请
    STORAGE DEVICE 审中-公开

    公开(公告)号：US20180277597A1

    公开(公告)日：2018-09-27

    申请号：US15696875

    申请日：2017-09-06

    Applicant: TOSHIBA MEMORY CORPORATION

    Inventor： Yusuke ARAYASHIKI ,  Kouji MATSUO

    IPC: H01L27/24 ,  H01L45/00

    CPC classification number: H01L27/249 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/065 ,  H01L45/1226 ,  H01L45/1246 ,  H01L45/1253 ,  H01L45/144 ,  H01L45/1616 ,  H01L45/1675 ,  H01L45/1683

    Abstract: A storage device includes a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, and a sixth conductive layer. The storage device further includes a first variable resistance layer provided between the first and fifth conductive layers, a second variable resistance layer provided between the second and fifth conductive layers, a third variable resistance layer provided between the third and fifth conductive layers, and a fourth variable resistance layer provided between the first and sixth conductive layers. A first distance between the first and second variable resistance layers is shorter than a second distance between a portion of the first conductive layer and a portion of the second conductive layer which face each other across a region between the fifth and sixth conductive layers.

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