公开(公告)号：US20190287979A1

公开(公告)日：2019-09-19

申请号：US16122541

申请日：2018-09-05

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Kana HIRAYAMA ,  Kazuhiko YAMAMOTO ,  Kunifumi SUZUKI

IPC: H01L27/115 ,  G11C7/06 ,  G11C8/10 ,  G11C16/08 ,  G11C16/24 ,  G11C16/04

Abstract: A nonvolatile semiconductor memory device includes a first wiring layer, multiple second wiring layers provided above the first wiring layer and arrayed along a direction perpendicular to a semiconductor substrate, a semiconductor layer extending along the direct ion and electrically connected to the first wiring layer, a first insulating layer extending along the direction and provided between the semiconductor layer and the multiple second wiring layers, a first oxide layer extending along the direction and provided between the first insulating layer and the multiple second wiring layers, and multiple second oxide layers having first sides being respectively in contact with the multiple second wiring layers and having second sides being in contact with the first oxide layer, a resistance value of a stacked film configured with the first oxide layer and the multiple second oxide layers varying according to a voltage being applied to the multiple second wiring layers.

公开(公告)号：US20180277205A1

公开(公告)日：2018-09-27

申请号：US15696118

申请日：2017-09-05

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Kunifumi SUZUKI ,  Kazuhiko Yamamoto

IPC: G11C13/00 ,  H01L45/00 ,  H01L27/24

Abstract: A memory device includes a control circuit configured to (i) start a first application of a first voltage between a first conductive layer and a third conductive layer, (ii) start a second application of the first voltage between a second conductive layer and the third conductive layer after a lapse of a first delay time since the start of the first application of the first voltage, and (iii) start an application of a second voltage, which is smaller than the first voltage, between the first conductive layer and the third conductive layer after a lapse of a second delay time since the start of the second application of the first voltage between the second conductive layer and the third conductive layer.

公开(公告)号：US20190156888A1

公开(公告)日：2019-05-23

申请号：US16252629

申请日：2019-01-19

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Kunifumi SUZUKI ,  Kazuhiko YAMAMOTO

IPC: G11C13/00

Abstract: According to embodiments, a semiconductor memory device includes a first electrode, a second electrode, a memory cell, and a control circuit. The memory cell is provided between the first electrode and the second electrode and includes a metal film and a resistance change film. The control circuit applies a voltage between the first electrode and the second electrode to perform transition of a resistive state of the memory cell. The control circuit performs a first writing operation by applying a first pulse having a voltage of a first polarity to the memory cell and applying a second pulse having a voltage of the first polarity smaller than the voltage of the first pulse to the memory cell continuously after applying the first pulse.

公开(公告)号：US20190074438A1

公开(公告)日：2019-03-07

申请号：US15916805

申请日：2018-03-09

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Kazuhiko YAMAMOTO ,  Kunifumi SUZUKI ,  Tomotaka ARIGA

IPC: H01L45/00

Abstract: A memory device includes a crystal-including layer including a first metal, and a germanium-and-oxygen including layer contacting the crystal-including layer. At least a portion of the crystal-including layer is crystallized. The germanium-and-oxygen including layer includes germanium and oxygen.

公开(公告)号：US20200303006A1

公开(公告)日：2020-09-24

申请号：US16558905

申请日：2019-09-03

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Kunifumi SUZUKI

IPC: G11C13/00 ,  H01L27/24 ,  H01L45/00

Abstract: A storage device includes a first layer extending in a first direction, a second layer extending in a second direction intersecting the first direction, a third layer extending in a third direction intersecting the first and second directions, a first transistor including a first gate electrode electrically connected to the second layer, a first selection transistor having a first end electrically connected to the third layer and a second end electrically connected to the second layer, a first cell including a first element electrically connected between the first and second layers and to a node of the second layer that is between the first gate electrode of the first transistor and the second end of the first selection transistor, and a circuit turning on the first selection transistor to electrically connect the first cell to the third layer during a write operation performed on the first cell.

公开(公告)号：US20190287996A1

公开(公告)日：2019-09-19

申请号：US16122842

申请日：2018-09-05

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Kunifumi SUZUKI ,  Kazuhiko YAMAMOTO

IPC: H01L27/11582 ,  H01L27/1157 ,  G11C7/06 ,  G11C16/26 ,  G11C16/14 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a first interconnect layer provided above a semiconductor substrate; a plurality of second interconnect layers provided above the first interconnect layer; a semiconductor layer electrically coupled to the first interconnect layer; a first insulating layer provided between the semiconductor layer and the plurality of second interconnect layers; and a plurality of first oxide layers in which one side of the first oxide layers is in contact with the plurality of second interconnect layers while the other side of the first oxide layers is in contact with the first insulating layer, and a voltage is applied to the plurality of second interconnect layers to vary a resistance value.

公开(公告)号：US20180301190A1

公开(公告)日：2018-10-18

申请号：US16011923

申请日：2018-06-19

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Kunifumi SUZUKI ,  Kazuhiko YAMAMOTO

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0064 ,  G11C2013/0092 ,  G11C2213/11 ,  G11C2213/33 ,  G11C2213/34 ,  G11C2213/77

Abstract: According to embodiments, a semiconductor memory device includes a first electrode, a second electrode, a memory cell, and a control circuit. The memory cell is provided between the first electrode and the second electrode and includes a metal film and a resistance change film. The control circuit applies a voltage between the first electrode and the second electrode to perform transition of a resistive state of the memory cell. The control circuit performs a first writing operation by applying a first pulse having a voltage of a first polarity to the memory cell and applying a second pulse having a voltage of the first polarity smaller than the voltage of the first pulse to the memory cell continuously after applying the first pulse.

公开(公告)号：US20210013229A1

公开(公告)日：2021-01-14

申请号：US17028748

申请日：2020-09-22

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Haruka SAKUMA ,  Hidenori MIYAGAWA ,  Shosuke FUJI ,  Kiwamu SAKUMA ,  Fumitaka ARAI ,  Kunifumi SUZUKI

IPC: H01L27/11597 ,  H01L27/1159 ,  H01L29/51 ,  H01L21/28

Abstract: A semiconductor memory device comprises: a substrate; a first semiconductor portion provided separated from the substrate in a first direction intersecting a surface of the substrate, the first semiconductor portion extending in a second direction intersecting the first direction; a first gate electrode extending in the first direction; a first insulating portion which is provided between the first semiconductor portion and the first gate electrode, includes hafnium (Hf) and oxygen (O), and includes an orthorhombic crystal as a crystal structure; a first conductive portion provided between the first semiconductor portion and the first insulating portion; and a second insulating portion provided between the first semiconductor portion and the first conductive portion. An area of a facing surface of the first conductive portion facing the first semiconductor portion is larger than an area of a facing surface of the first conductive portion facing the first gate electrode.

公开(公告)号：US20200091171A1

公开(公告)日：2020-03-19

申请号：US16267878

申请日：2019-02-05

Applicant: Toshiba Memory Corporation

Inventor： Hiroki TOKUHIRA ,  Kazuhiko YAMAMOTO ,  Kunifumi SUZUKI

IPC: H01L27/11582 ,  H01L29/51

Abstract: A semiconductor memory device includes a stacked body including insulating layers and gate electrode layers alternately stacked in a direction, a semiconductor layer extending in the direction, and a gate insulating layer provided between the semiconductor layer and the gate electrode layer, and including a first layer, a second layer, and a third layer between the first layer and the second layer. The first layer includes a first insulator, the second layer includes at least one oxide selected from aluminum oxide, yttrium oxide, lanthanum oxide, gadolinium oxide, ytterbium oxide, hafnium oxide, and zirconium oxide, the third layer includes at least one material selected from silicon, germanium, silicon germanium and silicon carbide, and the third layer is positioned between the semiconductor layer and the insulating layer.

公开(公告)号：US20190088716A1

公开(公告)日：2019-03-21

申请号：US15910690

申请日：2018-03-02

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Kunifumi SUZUKI ,  Kazuhiko YAMAMOTO

IPC: H01L27/24 ,  H01L45/00 ,  G11C13/00

CPC classification number: H01L27/249 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0078 ,  G11C2013/009 ,  G11C2213/32 ,  G11C2213/51 ,  G11C2213/71 ,  G11C2213/77 ,  H01L45/08 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1641

Abstract: A memory device is described. A first conductive layer extends in a first direction. A second conductive layer extends in the first direction. A third conductive layer extends in a second direction intersecting the first direction. A first oxide region is disposed between the first conductive layer and the third conductive layer and between the second conductive layer and the third conductive layer. A semiconductor region is disposed between the first conductive layer and the first oxide region and between the first conductive layer and the second conductive layer. A second distance between the semiconductor region, which is disposed between the first conductive layer and the second conductive layer, and the third conductive layer, is longer than a first distance between the semiconductor region, which is disposed between the first conductive layer and the first oxide region, and the third conductive layer.