公开(公告)号：US11222901B2

公开(公告)日：2022-01-11

申请号：US16291960

申请日：2019-03-04

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Masaki Noguchi

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L21/02 ,  H01L21/28

Abstract: A semiconductor device includes a semiconductor layer, a charge storage layer provided on a surface of the semiconductor layer via a tunnel insulating film, and an electrode layer provided on a surface of the charge storage layer via a block insulating film. The tunnel insulating film includes a plurality of first silicon oxynitride films which are provided between the semiconductor layer and the charge storage layer. The tunnel insulating film further includes a silicon oxide film provided between the first silicon oxynitride films and/or a second silicon oxynitride film which is provided between the first silicon oxynitride films and has an oxygen concentration higher than an oxygen concentration in the first silicon oxynitride film.

公开(公告)号：US11139378B2

公开(公告)日：2021-10-05

申请号：US16556034

申请日：2019-08-29

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Masaki Noguchi ,  Tatsunori Isogai ,  Tomonori Aoyama

IPC: H01L21/28 ,  H01L29/792 ,  H01L29/66 ,  H01L27/11578 ,  H01L27/1157

Abstract: According to one embodiment, a semiconductor device includes a semiconductor layer, a charge storage layer provided on the surface of the semiconductor layer via a first insulating film, and an electrode layer provided on the surface of the charge storage layer via a second insulating film. The first insulating film includes a first region where the compositional ratio of nitrogen to silicon, oxygen and nitrogen varies from a first value to a second value, which is lower than the first value, along a first direction from the semiconductor layer toward the charge storage layer.

公开(公告)号：US10741383B2

公开(公告)日：2020-08-11

申请号：US16123615

申请日：2018-09-06

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Masaki Noguchi ,  Tatsunori Isogai ,  Tomonori Aoyama

IPC: H01L21/02 ,  H01L27/11582 ,  H01L21/28

Abstract: In one embodiment, a method of manufacturing a semiconductor device includes alternately forming a plurality of first films and a plurality of second films on a substrate, and forming an opening in the first and second films. The method further includes sequentially forming a first insulator, a charge storage layer, a second insulator and a semiconductor layer on surfaces of the first and second films in the opening. The second insulator includes a silicon oxynitride film, and the silicon oxynitride film is formed using a first gas that includes silicon and a first element, a second gas that includes oxygen and nitrogen, and a third gas that includes a second element that reacts with the first element.

公开(公告)号：US10153262B2

公开(公告)日：2018-12-11

申请号：US15699609

申请日：2017-09-08

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Tatsunori Isogai ,  Masaki Noguchi

IPC: H01L27/02 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11582 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11556

Abstract: According to an embodiment, a semiconductor device includes: a stacked body in which insulator layers and conductor layers alternately stacked; a block insulator film on a surface of the insulator layer and a surface of the conductor layer; a charge storage capacitor film on a surface of the block insulator film; a tunnel insulator film including a first insulator film on a surface of the charge storage capacitor film, a second insulator film on a surface of the first insulator film, and a third insulator film on a surface of the second insulator film; and a channel film on a surface of the third insulator film. A defect termination element is included in at least the first or the third insulator film, and defect termination element content concentrations of the first, the second, and the third insulator film are different from one another.

公开(公告)号：US10403642B2

公开(公告)日：2019-09-03

申请号：US16056941

申请日：2018-08-07

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Kazuhiro Matsuo ,  Akiko Sekihara ,  Akira Takashima ,  Tomonori Aoyama ,  Tatsunori Isogai ,  Masaki Noguchi

IPC: H01L29/792 ,  H01L27/11582 ,  H01L29/51

Abstract: A semiconductor device includes a semiconductor layer, a first conductive layer, a tunneling insulating film, and a charge trapping film. The tunneling insulating film is provided between the semiconductor layer and the first conductive layer. The charge trapping film is provided between the first conductive layer and the tunneling insulating film. The charge trapping film includes a first separation layer, a first trapping layer, and a second trapping layer. The first trapping layer is positioned between the tunneling insulating film and the first separation layer. The second trapping layer is positioned between the first conductive layer and the first separation layer. A trapping efficiency of charge in the first trapping layer is higher than a trapping efficiency of charge in the second trapping layer.

公开(公告)号：US20190139981A1

公开(公告)日：2019-05-09

申请号：US16056941

申请日：2018-08-07

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Kazuhiro Matsuo ,  Akiko Sekihara ,  Akira Takashima ,  Tomonori Aoyama ,  Tatsunori Isogai ,  Masaki Noguchi

IPC: H01L27/11582 ,  H01L29/51

CPC classification number: H01L27/11582 ,  H01L29/40117 ,  H01L29/518

Abstract: A semiconductor device includes a semiconductor layer, a first conductive layer, a tunneling insulating film, and a charge trapping film. The tunneling insulating film is provided between the semiconductor layer and the first conductive layer. The charge trapping film is provided between the first conductive layer and the tunneling insulating film. The charge trapping film includes a first separation layer, a first trapping layer, and a second trapping layer. The first trapping layer is positioned between the tunneling insulating film and the first separation layer. The second trapping layer is positioned between the first conductive layer and the first separation layer. A trapping efficiency of charge in the first trapping layer is higher than a trapping efficiency of charge in the second trapping layer.