公开(公告)号：US10964716B2

公开(公告)日：2021-03-30

申请号：US16275509

申请日：2019-02-14

Applicant: Toshiba Memory Corporation

Inventor： Shinji Mori ,  Kazuhiro Matsuo ,  Yuta Saito ,  Keiichi Sawa ,  Kazuhisa Matsuda ,  Atsushi Takahashi ,  Masayuki Tanaka ,  Kenichiro Toratani

IPC: H01L27/11582 ,  H01L21/28 ,  H01L21/3065 ,  H01L21/311 ,  H01L29/423

Abstract: A semiconductor device comprises a substrate. A plurality of electrode layers and a plurality of insulating layers are formed in an alternating stack above the substrate. A semiconductor column extends through the plurality of electrode layers and the plurality of insulating layers. The semiconductor column comprises a single-crystal semiconductor material on an outer peripheral surface facing the electrode and insulating layers. First insulating films are formed between the semiconductor column and the electrode layers. The first insulating films are spaced from each other along the column length. Each first insulating film corresponds to one electrode layer. A charge storage layer is between each of the first insulating films and the electrode layers. A second insulating film is between the charge storage layer and each of the electrode layers.

公开(公告)号：US10910401B2

公开(公告)日：2021-02-02

申请号：US16559165

申请日：2019-09-03

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Keiichi Sawa ,  Kazuhiro Matsuo ,  Kazuhisa Matsuda ,  Hiroyuki Yamashita ,  Yuta Saito ,  Shinji Mori ,  Masayuki Tanaka ,  Kenichiro Toratani ,  Atsushi Takahashi ,  Shouji Honda

IPC: H01L27/11582 ,  H01L29/792 ,  H01L27/11578 ,  H01L27/11519 ,  H01L27/1157

Abstract: In one embodiment, a semiconductor device includes a substrate, insulating films and first films alternately stacked on the substrate, at least one of the first films including an electrode layer and a charge storage layer provided on a face of the electrode layer via a first insulator, and a semiconductor layer provided on a face of the charge storage layer via a second insulator. The device further includes at least one of a first portion including nitrogen and provided between the first insulator and the charge storage layer with an air gap provided in the first insulator, a second portion including nitrogen, provided between the charge storage layer and the second insulator, and including a portion protruding toward the charge storage layer, and a third portion including nitrogen and provided between the second insulator and the semiconductor layer with an air gap provided in the first insulator.

公开(公告)号：US10304850B2

公开(公告)日：2019-05-28

申请号：US15011911

申请日：2016-02-01

Applicant: Toshiba Memory Corporation

Inventor： Kazuhiro Matsuo ,  Masayuki Tanaka ,  Shinji Mori ,  Kenichiro Toratani

IPC: H01L27/115 ,  H01L29/792 ,  H01L27/11582 ,  H01L49/02

Abstract: A semiconductor memory device according to an embodiment includes a substrate, a stacked body provided on the substrate, a plurality of electrode films being stacked to be separated from each other in the stacked body, a semiconductor pillar piercing the plurality of electrode films, a first insulating film provided between the semiconductor pillar and the electrode films, a second insulating film provided between the semiconductor pillar and the first insulating film; and a third insulating film provided between the first insulating film and the electrode films. The first insulating film includes silicon, nitrogen, oxygen, and carbon.

公开(公告)号：US20190139981A1

公开(公告)日：2019-05-09

申请号：US16056941

申请日：2018-08-07

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Kazuhiro Matsuo ,  Akiko Sekihara ,  Akira Takashima ,  Tomonori Aoyama ,  Tatsunori Isogai ,  Masaki Noguchi

IPC: H01L27/11582 ,  H01L29/51

CPC classification number: H01L27/11582 ,  H01L29/40117 ,  H01L29/518

Abstract: A semiconductor device includes a semiconductor layer, a first conductive layer, a tunneling insulating film, and a charge trapping film. The tunneling insulating film is provided between the semiconductor layer and the first conductive layer. The charge trapping film is provided between the first conductive layer and the tunneling insulating film. The charge trapping film includes a first separation layer, a first trapping layer, and a second trapping layer. The first trapping layer is positioned between the tunneling insulating film and the first separation layer. The second trapping layer is positioned between the first conductive layer and the first separation layer. A trapping efficiency of charge in the first trapping layer is higher than a trapping efficiency of charge in the second trapping layer.

公开(公告)号：US10403642B2

公开(公告)日：2019-09-03

申请号：US16056941

申请日：2018-08-07

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Kazuhiro Matsuo ,  Akiko Sekihara ,  Akira Takashima ,  Tomonori Aoyama ,  Tatsunori Isogai ,  Masaki Noguchi

IPC: H01L29/792 ,  H01L27/11582 ,  H01L29/51

Abstract: A semiconductor device includes a semiconductor layer, a first conductive layer, a tunneling insulating film, and a charge trapping film. The tunneling insulating film is provided between the semiconductor layer and the first conductive layer. The charge trapping film is provided between the first conductive layer and the tunneling insulating film. The charge trapping film includes a first separation layer, a first trapping layer, and a second trapping layer. The first trapping layer is positioned between the tunneling insulating film and the first separation layer. The second trapping layer is positioned between the first conductive layer and the first separation layer. A trapping efficiency of charge in the first trapping layer is higher than a trapping efficiency of charge in the second trapping layer.

公开(公告)号：US10396280B2

公开(公告)日：2019-08-27

申请号：US15695996

申请日：2017-09-05

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Shinji Mori ,  Masayuki Tanaka ,  Kazuhiro Matsuo ,  Kenichiro Toratani ,  Keiichi Sawa ,  Kazuhisa Matsuda ,  Atsushi Takahashi ,  Yuta Saito

IPC: H01L45/00 ,  H01L27/24

Abstract: A semiconductor memory device includes a plurality of first interconnections extending in a first direction, and a second interconnection extending in a second direction different from the first direction. The device further includes a resistance change film provided between the plurality of first interconnections and the second interconnection, the resistance change film including (a) silicon and a semiconductor layer including one or more elements selected from among oxygen, carbon, nitrogen, phosphorus, boron, and germanium, or (b) a first layer containing the germanium and a second layer containing the silicon.

公开(公告)号：US20190027538A1

公开(公告)日：2019-01-24

申请号：US15892016

申请日：2018-02-08

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Keiichi Sawa ,  Kazuhisa Matsuda ,  Atsushi Takahashi ,  Takaumi Morita ,  Masayuki Tanaka ,  Shinji Mori ,  Kazuhiro Matsuo ,  Yuta Saito ,  Kenichiro Toratani ,  Hisashi Okuchi

IPC: H01L27/24 ,  G11C13/00 ,  H01L45/00

Abstract: In one embodiment, a semiconductor storage device includes a first interconnect extending in a first direction, a plurality of second interconnects extending in a second direction different from the first direction, and a plurality of first insulators provided alternately with the second interconnects. The device further includes a resistance change film provided between the first interconnect and at least one of the second interconnects and including a first metal layer or a first semiconductor layer that includes a first face provided on a first interconnect side and a second face provided on a second interconnect side, at least any of the first face and the second face having a curved plane shape.

公开(公告)号：US10927457B2

公开(公告)日：2021-02-23

申请号：US14847487

申请日：2015-09-08

Applicant: Toshiba Memory Corporation

Inventor： Koji Nakahara ,  Kazuhiro Matsuo

IPC: C23C16/44 ,  B01D50/00 ,  F23J15/02 ,  B01D29/48 ,  B01D47/10 ,  B01D29/23

Abstract: A semiconductor manufacturing apparatus in this embodiment includes a reactor, a pump, an exhaust pipe and a mesh member. The reactor houses a semiconductor substrate to treat the semiconductor substrate. The pump exhausts a gas inside the reactor. The exhaust pipe connects between the reactor and the pump. The mesh member is located at a flow inlet of the pump for the gas or in the exhaust pipe and has a main plane having a plurality of meshes arranged thereon. The mesh member has a protrusion and/or protruding shape projecting upstream of the gas.

公开(公告)号：US10923487B2

公开(公告)日：2021-02-16

申请号：US16287914

申请日：2019-02-27

Applicant: Toshiba Memory Corporation

Inventor： Hiroyuki Yamashita ,  Shinji Mori ,  Keiichi Sawa ,  Kazuhiro Matsuo ,  Kazuhisa Matsuda ,  Yuta Saito ,  Atsushi Takahashi ,  Masayuki Tanaka

IPC: H01L27/11556 ,  H01L27/11582

Abstract: A semiconductor memory device includes a channel layer and a gate electrode. A first insulating layer is between the semiconductor layer and the gate electrode. A second insulating layer is between the first insulating layer and the gate electrode. A storage region is between the first insulating layer and the second insulating layer. The storage region comprises metal or semiconductor material. A coating layer comprises silicon and nitrogen and surrounds the storage region. The coating layer is between the storage region and the second insulating layer and between the storage region and the first insulating layer.

公开(公告)号：US10777573B2

公开(公告)日：2020-09-15

申请号：US16285068

申请日：2019-02-25

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Yuta Saito ,  Shinji Mori ,  Keiichi Sawa ,  Kazuhisa Matsuda ,  Kazuhiro Matsuo ,  Hiroyuki Yamashita

IPC: H01L27/11582 ,  H01L21/324 ,  H01L23/532 ,  H01L21/28

Abstract: A semiconductor device includes a semiconductor layer containing metal atoms, a charge storage layer provided on a surface of the semiconductor layer via a first insulating film, and an electrode layer provided on a surface of the charge storage layer via a second insulating film. The thickness of the first insulating film is 5 nm or more and 10 nm or less. The concentration of the metal atoms in the semiconductor layer is 5.0×1017 [EA/cm3] or higher and 1.3×1020 [EA/cm3] or lower.