公开(公告)号：US10593542B2

公开(公告)日：2020-03-17

申请号：US15695203

申请日：2017-09-05

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Takashi Furuhashi ,  Masayuki Tanaka ,  Shinji Mori ,  Kenichiro Toratani

IPC: H01L21/02 ,  H01L21/67 ,  H01L21/28 ,  H01L27/11582

Abstract: According to an embodiment, a manufacturing method of a semiconductor device includes: carrying a substrate alternately stacked an electrode layer and an insulation layer into a chamber; increasing the temperature in the chamber to a predetermined temperature; and supplying hydrogen and material gas including metal simultaneously into the chamber, and supplying oxidizing gas the partial pressure ratio of which to the hydrogen is set so as to provide an atmosphere of reducing the electrode layer, by using an ALD method, and thereby forming, on a surface of the electrode layer and a surface of the insulation layer, a metal oxide layer obtained by oxidizing the metal.

公开(公告)号：US10283646B2

公开(公告)日：2019-05-07

申请号：US15454618

申请日：2017-03-09

Applicant: Toshiba Memory Corporation

Inventor： Keiichi Sawa ,  Shinji Mori ,  Masayuki Tanaka ,  Kenichiro Toratani ,  Takashi Furuhashi

IPC: H01L29/788 ,  H01L27/11521 ,  H01L27/11556 ,  H01L29/167 ,  H01L29/49 ,  H01L29/66 ,  H01L21/28 ,  H01L29/792

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes first and second gate electrode layers, an inter-layer insulating layer, a channel layer, a tunneling insulating layer, first and second charge storage portions, and a blocking insulating layer. The channel layer is separated from the first and second gate electrode layers, and the inter-layer insulating layer. The tunneling insulating layer is provided between the first gate electrode layer and the channel layer. The first charge storage portion is provided between the first gate electrode layer and the tunneling insulating layer. The second charge storage portion is provided the second gate electrode layer and the tunneling insulating layer. The blocking insulating layer is provided between the inter-layer insulating layer and the tunneling insulating layer, between the first gate electrode layer and the first charge storage portion, between the inter-layer insulating layer and the first charge storage portion.