公开(公告)号：US09892930B1

公开(公告)日：2018-02-13

申请号：US15412396

申请日：2017-01-23

Applicant: Toshiba Memory Corporation

Inventor： Keiichi Sawa ,  Shinji Mori ,  Masayuki Tanaka ,  Katsuyuki Kitamoto

IPC: H01L27/115 ,  H01L21/28 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L21/28282 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/1157 ,  H01L27/11582

Abstract: A semiconductor memory device includes a first electrode layer; a second electrode layer provided above the first electrode layer; a first insulating oxide layer provided between the first and second electrode layers; a semiconductor layer extending through the first electrode layer, the first insulating oxide layer and the second electrode layer that are stacked in the first direction; and a second insulating oxide layer extending in the first direction between the semiconductor layer and the first insulating oxide layer, the second insulating oxide layer being in contact with the first insulating oxide layer. At least one of the first insulating oxide layer and the second insulating oxide layer includes nitrogen atoms. The nitrogen atoms are distributed around an interface between the first insulating oxide layer and the second insulating oxide layer, or distributed in the vicinity of the interface.

公开(公告)号：US10964716B2

公开(公告)日：2021-03-30

申请号：US16275509

申请日：2019-02-14

Applicant: Toshiba Memory Corporation

Inventor： Shinji Mori ,  Kazuhiro Matsuo ,  Yuta Saito ,  Keiichi Sawa ,  Kazuhisa Matsuda ,  Atsushi Takahashi ,  Masayuki Tanaka ,  Kenichiro Toratani

IPC: H01L27/11582 ,  H01L21/28 ,  H01L21/3065 ,  H01L21/311 ,  H01L29/423

Abstract: A semiconductor device comprises a substrate. A plurality of electrode layers and a plurality of insulating layers are formed in an alternating stack above the substrate. A semiconductor column extends through the plurality of electrode layers and the plurality of insulating layers. The semiconductor column comprises a single-crystal semiconductor material on an outer peripheral surface facing the electrode and insulating layers. First insulating films are formed between the semiconductor column and the electrode layers. The first insulating films are spaced from each other along the column length. Each first insulating film corresponds to one electrode layer. A charge storage layer is between each of the first insulating films and the electrode layers. A second insulating film is between the charge storage layer and each of the electrode layers.

公开(公告)号：US10910401B2

公开(公告)日：2021-02-02

申请号：US16559165

申请日：2019-09-03

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Keiichi Sawa ,  Kazuhiro Matsuo ,  Kazuhisa Matsuda ,  Hiroyuki Yamashita ,  Yuta Saito ,  Shinji Mori ,  Masayuki Tanaka ,  Kenichiro Toratani ,  Atsushi Takahashi ,  Shouji Honda

IPC: H01L27/11582 ,  H01L29/792 ,  H01L27/11578 ,  H01L27/11519 ,  H01L27/1157

Abstract: In one embodiment, a semiconductor device includes a substrate, insulating films and first films alternately stacked on the substrate, at least one of the first films including an electrode layer and a charge storage layer provided on a face of the electrode layer via a first insulator, and a semiconductor layer provided on a face of the charge storage layer via a second insulator. The device further includes at least one of a first portion including nitrogen and provided between the first insulator and the charge storage layer with an air gap provided in the first insulator, a second portion including nitrogen, provided between the charge storage layer and the second insulator, and including a portion protruding toward the charge storage layer, and a third portion including nitrogen and provided between the second insulator and the semiconductor layer with an air gap provided in the first insulator.

公开(公告)号：US10593542B2

公开(公告)日：2020-03-17

申请号：US15695203

申请日：2017-09-05

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Takashi Furuhashi ,  Masayuki Tanaka ,  Shinji Mori ,  Kenichiro Toratani

IPC: H01L21/02 ,  H01L21/67 ,  H01L21/28 ,  H01L27/11582

Abstract: According to an embodiment, a manufacturing method of a semiconductor device includes: carrying a substrate alternately stacked an electrode layer and an insulation layer into a chamber; increasing the temperature in the chamber to a predetermined temperature; and supplying hydrogen and material gas including metal simultaneously into the chamber, and supplying oxidizing gas the partial pressure ratio of which to the hydrogen is set so as to provide an atmosphere of reducing the electrode layer, by using an ALD method, and thereby forming, on a surface of the electrode layer and a surface of the insulation layer, a metal oxide layer obtained by oxidizing the metal.

公开(公告)号：US10304850B2

公开(公告)日：2019-05-28

申请号：US15011911

申请日：2016-02-01

Applicant: Toshiba Memory Corporation

Inventor： Kazuhiro Matsuo ,  Masayuki Tanaka ,  Shinji Mori ,  Kenichiro Toratani

IPC: H01L27/115 ,  H01L29/792 ,  H01L27/11582 ,  H01L49/02

Abstract: A semiconductor memory device according to an embodiment includes a substrate, a stacked body provided on the substrate, a plurality of electrode films being stacked to be separated from each other in the stacked body, a semiconductor pillar piercing the plurality of electrode films, a first insulating film provided between the semiconductor pillar and the electrode films, a second insulating film provided between the semiconductor pillar and the first insulating film; and a third insulating film provided between the first insulating film and the electrode films. The first insulating film includes silicon, nitrogen, oxygen, and carbon.

公开(公告)号：US10923487B2

公开(公告)日：2021-02-16

申请号：US16287914

申请日：2019-02-27

Applicant: Toshiba Memory Corporation

Inventor： Hiroyuki Yamashita ,  Shinji Mori ,  Keiichi Sawa ,  Kazuhiro Matsuo ,  Kazuhisa Matsuda ,  Yuta Saito ,  Atsushi Takahashi ,  Masayuki Tanaka

IPC: H01L27/11556 ,  H01L27/11582

Abstract: A semiconductor memory device includes a channel layer and a gate electrode. A first insulating layer is between the semiconductor layer and the gate electrode. A second insulating layer is between the first insulating layer and the gate electrode. A storage region is between the first insulating layer and the second insulating layer. The storage region comprises metal or semiconductor material. A coating layer comprises silicon and nitrogen and surrounds the storage region. The coating layer is between the storage region and the second insulating layer and between the storage region and the first insulating layer.

公开(公告)号：US10522596B2

公开(公告)日：2019-12-31

申请号：US15892016

申请日：2018-02-08

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Keiichi Sawa ,  Kazuhisa Matsuda ,  Atsushi Takahashi ,  Takaumi Morita ,  Masayuki Tanaka ,  Shinji Mori ,  Kazuhiro Matsuo ,  Yuta Saito ,  Kenichiro Toratani ,  Hisashi Okuchi

IPC: H01L27/24 ,  G11C13/00 ,  H01L27/108 ,  H01L45/00

Abstract: In one embodiment, a semiconductor storage device includes a first interconnect extending in a first direction, a plurality of second interconnects extending in a second direction different from the first direction, and a plurality of first insulators provided alternately with the second interconnects. The device further includes a resistance change film provided between the first interconnect and at least one of the second interconnects and including a first metal layer or a first semiconductor layer that includes a first face provided on a first interconnect side and a second face provided on a second interconnect side, at least any of the first face and the second face having a curved plane shape.

公开(公告)号：US10283646B2

公开(公告)日：2019-05-07

申请号：US15454618

申请日：2017-03-09

Applicant: Toshiba Memory Corporation

Inventor： Keiichi Sawa ,  Shinji Mori ,  Masayuki Tanaka ,  Kenichiro Toratani ,  Takashi Furuhashi

IPC: H01L29/788 ,  H01L27/11521 ,  H01L27/11556 ,  H01L29/167 ,  H01L29/49 ,  H01L29/66 ,  H01L21/28 ,  H01L29/792

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes first and second gate electrode layers, an inter-layer insulating layer, a channel layer, a tunneling insulating layer, first and second charge storage portions, and a blocking insulating layer. The channel layer is separated from the first and second gate electrode layers, and the inter-layer insulating layer. The tunneling insulating layer is provided between the first gate electrode layer and the channel layer. The first charge storage portion is provided between the first gate electrode layer and the tunneling insulating layer. The second charge storage portion is provided the second gate electrode layer and the tunneling insulating layer. The blocking insulating layer is provided between the inter-layer insulating layer and the tunneling insulating layer, between the first gate electrode layer and the first charge storage portion, between the inter-layer insulating layer and the first charge storage portion.

公开(公告)号：US20180261445A1

公开(公告)日：2018-09-13

申请号：US15695203

申请日：2017-09-05

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Takashi FURUHASHI ,  Masayuki Tanaka ,  Shinji Mori ,  Kenichiro Toratani

IPC: H01L21/02 ,  H01L21/67 ,  H01L21/28

Abstract: According to an embodiment, a manufacturing method of a semiconductor device includes: carrying a substrate alternately stacked an electrode layer and an insulation layer into a chamber; increasing the temperature in the chamber to a predetermined temperature; and supplying hydrogen and material gas including metal simultaneously into the chamber, and supplying oxidizing gas the partial pressure ratio of which to the hydrogen is set so as to provide an atmosphere of reducing the electrode layer, by using an ALD method, and thereby forming, on a surface of the electrode layer and a surface of the insulation layer, a metal oxide layer obtained by oxidizing the metal.

公开(公告)号：US10396280B2

公开(公告)日：2019-08-27

申请号：US15695996

申请日：2017-09-05

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Shinji Mori ,  Masayuki Tanaka ,  Kazuhiro Matsuo ,  Kenichiro Toratani ,  Keiichi Sawa ,  Kazuhisa Matsuda ,  Atsushi Takahashi ,  Yuta Saito

IPC: H01L45/00 ,  H01L27/24

Abstract: A semiconductor memory device includes a plurality of first interconnections extending in a first direction, and a second interconnection extending in a second direction different from the first direction. The device further includes a resistance change film provided between the plurality of first interconnections and the second interconnection, the resistance change film including (a) silicon and a semiconductor layer including one or more elements selected from among oxygen, carbon, nitrogen, phosphorus, boron, and germanium, or (b) a first layer containing the germanium and a second layer containing the silicon.