公开(公告)号：US10043864B2

公开(公告)日：2018-08-07

申请号：US15223632

申请日：2016-07-29

Applicant: Toshiba Memory Corporation

Inventor： Minoru Oda ,  Shinji Mori ,  Kiwamu Sakuma ,  Masumi Saitoh

IPC: H01L29/76 ,  H01L29/04 ,  H01L29/786 ,  H01L29/66 ,  H01L29/78

Abstract: According to one embodiment, a semiconductor device includes a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, and a first electrode. The third semiconductor layer is provided between the first semiconductor layer and the second semiconductor layer. The first electrode opposes the third semiconductor layer. An orientation ratio of the third semiconductor layer is higher than an orientation ratio of the first semiconductor layer.

公开(公告)号：US10020364B2

公开(公告)日：2018-07-10

申请号：US14849748

申请日：2015-09-10

Applicant: Toshiba Memory Corporation

Inventor： Hiroyuki Yamasaki ,  Makoto Fujiwara ,  Shinji Mori

IPC: H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/336 ,  H01L29/10 ,  H01L27/11582 ,  H01L21/324 ,  H01L21/28

CPC classification number: H01L29/1054 ,  H01L21/324 ,  H01L27/11582 ,  H01L29/40117

Abstract: One embodiment includes: forming a laminated body by alternately laminating a conducting layer and an interlayer insulating layer on a substrate; forming a memory hole passing through the laminated body; forming a memory gate insulating layer including a charge storage layer on an inner wall of the memory hole; forming a first semiconductor layer on the memory gate insulating layer; forming a cover film on the first semiconductor layer; removing the memory gate insulating layer, the first semiconductor layer, and the cover film on a bottom surface of the memory hole, to expose the substrate; forming an epitaxial layer on the exposed substrate; removing the cover film; and forming the second semiconductor layer along the first semiconductor layer, to electrically couple: the substrate to the first semiconductor layer; and the substrate to the second semiconductor layer, via the epitaxial layer.

公开(公告)号：US10923487B2

公开(公告)日：2021-02-16

申请号：US16287914

申请日：2019-02-27

Applicant: Toshiba Memory Corporation

Inventor： Hiroyuki Yamashita ,  Shinji Mori ,  Keiichi Sawa ,  Kazuhiro Matsuo ,  Kazuhisa Matsuda ,  Yuta Saito ,  Atsushi Takahashi ,  Masayuki Tanaka

IPC: H01L27/11556 ,  H01L27/11582

Abstract: A semiconductor memory device includes a channel layer and a gate electrode. A first insulating layer is between the semiconductor layer and the gate electrode. A second insulating layer is between the first insulating layer and the gate electrode. A storage region is between the first insulating layer and the second insulating layer. The storage region comprises metal or semiconductor material. A coating layer comprises silicon and nitrogen and surrounds the storage region. The coating layer is between the storage region and the second insulating layer and between the storage region and the first insulating layer.

公开(公告)号：US10777573B2

公开(公告)日：2020-09-15

申请号：US16285068

申请日：2019-02-25

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Yuta Saito ,  Shinji Mori ,  Keiichi Sawa ,  Kazuhisa Matsuda ,  Kazuhiro Matsuo ,  Hiroyuki Yamashita

IPC: H01L27/11582 ,  H01L21/324 ,  H01L23/532 ,  H01L21/28

Abstract: A semiconductor device includes a semiconductor layer containing metal atoms, a charge storage layer provided on a surface of the semiconductor layer via a first insulating film, and an electrode layer provided on a surface of the charge storage layer via a second insulating film. The thickness of the first insulating film is 5 nm or more and 10 nm or less. The concentration of the metal atoms in the semiconductor layer is 5.0×1017 [EA/cm3] or higher and 1.3×1020 [EA/cm3] or lower.

公开(公告)号：US10522596B2

公开(公告)日：2019-12-31

申请号：US15892016

申请日：2018-02-08

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Keiichi Sawa ,  Kazuhisa Matsuda ,  Atsushi Takahashi ,  Takaumi Morita ,  Masayuki Tanaka ,  Shinji Mori ,  Kazuhiro Matsuo ,  Yuta Saito ,  Kenichiro Toratani ,  Hisashi Okuchi

IPC: H01L27/24 ,  G11C13/00 ,  H01L27/108 ,  H01L45/00

Abstract: In one embodiment, a semiconductor storage device includes a first interconnect extending in a first direction, a plurality of second interconnects extending in a second direction different from the first direction, and a plurality of first insulators provided alternately with the second interconnects. The device further includes a resistance change film provided between the first interconnect and at least one of the second interconnects and including a first metal layer or a first semiconductor layer that includes a first face provided on a first interconnect side and a second face provided on a second interconnect side, at least any of the first face and the second face having a curved plane shape.

公开(公告)号：US10283646B2

公开(公告)日：2019-05-07

申请号：US15454618

申请日：2017-03-09

Applicant: Toshiba Memory Corporation

Inventor： Keiichi Sawa ,  Shinji Mori ,  Masayuki Tanaka ,  Kenichiro Toratani ,  Takashi Furuhashi

IPC: H01L29/788 ,  H01L27/11521 ,  H01L27/11556 ,  H01L29/167 ,  H01L29/49 ,  H01L29/66 ,  H01L21/28 ,  H01L29/792

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes first and second gate electrode layers, an inter-layer insulating layer, a channel layer, a tunneling insulating layer, first and second charge storage portions, and a blocking insulating layer. The channel layer is separated from the first and second gate electrode layers, and the inter-layer insulating layer. The tunneling insulating layer is provided between the first gate electrode layer and the channel layer. The first charge storage portion is provided between the first gate electrode layer and the tunneling insulating layer. The second charge storage portion is provided the second gate electrode layer and the tunneling insulating layer. The blocking insulating layer is provided between the inter-layer insulating layer and the tunneling insulating layer, between the first gate electrode layer and the first charge storage portion, between the inter-layer insulating layer and the first charge storage portion.

公开(公告)号：US20180261445A1

公开(公告)日：2018-09-13

申请号：US15695203

申请日：2017-09-05

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Takashi FURUHASHI ,  Masayuki Tanaka ,  Shinji Mori ,  Kenichiro Toratani

IPC: H01L21/02 ,  H01L21/67 ,  H01L21/28

Abstract: According to an embodiment, a manufacturing method of a semiconductor device includes: carrying a substrate alternately stacked an electrode layer and an insulation layer into a chamber; increasing the temperature in the chamber to a predetermined temperature; and supplying hydrogen and material gas including metal simultaneously into the chamber, and supplying oxidizing gas the partial pressure ratio of which to the hydrogen is set so as to provide an atmosphere of reducing the electrode layer, by using an ALD method, and thereby forming, on a surface of the electrode layer and a surface of the insulation layer, a metal oxide layer obtained by oxidizing the metal.

公开(公告)号：US10396280B2

公开(公告)日：2019-08-27

申请号：US15695996

申请日：2017-09-05

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Shinji Mori ,  Masayuki Tanaka ,  Kazuhiro Matsuo ,  Kenichiro Toratani ,  Keiichi Sawa ,  Kazuhisa Matsuda ,  Atsushi Takahashi ,  Yuta Saito

IPC: H01L45/00 ,  H01L27/24

Abstract: A semiconductor memory device includes a plurality of first interconnections extending in a first direction, and a second interconnection extending in a second direction different from the first direction. The device further includes a resistance change film provided between the plurality of first interconnections and the second interconnection, the resistance change film including (a) silicon and a semiconductor layer including one or more elements selected from among oxygen, carbon, nitrogen, phosphorus, boron, and germanium, or (b) a first layer containing the germanium and a second layer containing the silicon.

公开(公告)号：US20190027538A1

公开(公告)日：2019-01-24

申请号：US15892016

申请日：2018-02-08

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Keiichi Sawa ,  Kazuhisa Matsuda ,  Atsushi Takahashi ,  Takaumi Morita ,  Masayuki Tanaka ,  Shinji Mori ,  Kazuhiro Matsuo ,  Yuta Saito ,  Kenichiro Toratani ,  Hisashi Okuchi

IPC: H01L27/24 ,  G11C13/00 ,  H01L45/00

Abstract: In one embodiment, a semiconductor storage device includes a first interconnect extending in a first direction, a plurality of second interconnects extending in a second direction different from the first direction, and a plurality of first insulators provided alternately with the second interconnects. The device further includes a resistance change film provided between the first interconnect and at least one of the second interconnects and including a first metal layer or a first semiconductor layer that includes a first face provided on a first interconnect side and a second face provided on a second interconnect side, at least any of the first face and the second face having a curved plane shape.

公开(公告)号：US10964716B2

公开(公告)日：2021-03-30

申请号：US16275509

申请日：2019-02-14

Applicant: Toshiba Memory Corporation

Inventor： Shinji Mori ,  Kazuhiro Matsuo ,  Yuta Saito ,  Keiichi Sawa ,  Kazuhisa Matsuda ,  Atsushi Takahashi ,  Masayuki Tanaka ,  Kenichiro Toratani

IPC: H01L27/11582 ,  H01L21/28 ,  H01L21/3065 ,  H01L21/311 ,  H01L29/423

Abstract: A semiconductor device comprises a substrate. A plurality of electrode layers and a plurality of insulating layers are formed in an alternating stack above the substrate. A semiconductor column extends through the plurality of electrode layers and the plurality of insulating layers. The semiconductor column comprises a single-crystal semiconductor material on an outer peripheral surface facing the electrode and insulating layers. First insulating films are formed between the semiconductor column and the electrode layers. The first insulating films are spaced from each other along the column length. Each first insulating film corresponds to one electrode layer. A charge storage layer is between each of the first insulating films and the electrode layers. A second insulating film is between the charge storage layer and each of the electrode layers.