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公开(公告)号：US10431297B2
公开(公告)日：2019-10-01
申请号：US16125601
申请日：2018-09-07
发明人： Noboru Shibata , Tomoharu Tanaka
摘要： A memory cell array is configured to have a plurality of memory cells arranged in a matrix, each of the memory cells being connected to a word line and a bit line and being capable of storing n values (n is a natural number equal to or larger than 3). A control circuit controls the potentials of the word line and bit line according to input data and writes data into a memory cell. The control circuit writes data into the memory cell to a k-valued threshold voltage (k
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2.发明申请公开(公告)号：US20190172530A1
公开(公告)日：2019-06-06
申请号：US16268726
申请日：2019-02-06
发明人： Tomoharu Tanaka , Jian Chen
IPC分类号： G11C11/56 , G11C16/34 , G11C16/10 , H01L27/11524 , H01L27/11521 , G11C16/04 , G11C16/12 , H01L27/115
摘要： A non-volatile semiconductor memory device includes an electrically data rewritable non-volatile semiconductor memory cell and a write circuit for writing data in the memory cell, the write circuit writing a data in the memory cells by supplying a write voltage Vpgm and a write control voltage VBL to the memory cell, continuing the writing of the data in the memory cell by changing the value of the write control voltage VBL in response to an advent of a first write state of the memory cell and inhibiting any operation of writing a data to the memory cell by further changing the value of the write control voltage VBL to Vdd in response to an advent of a second write state of the memory cell.
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公开(公告)号：US20190074057A1
公开(公告)日：2019-03-07
申请号：US16125601
申请日：2018-09-07
发明人： NOBORU SHIBATA , Tomoharu Tanaka
CPC分类号： G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/12 , G11C16/3454 , G11C16/3459 , G11C2211/5621 , G11C2211/5648
摘要： A memory cell array is configured to have a plurality of memory cells arranged in a matrix, each of the memory cells being connected to a word line and a bit line and being capable of storing n values (n is a natural number equal to or larger than 3). A control circuit controls the potentials of the word line and bit line according to input data and writes data into a memory cell. The control circuit writes data into the memory cell to a k-valued threshold voltage (k
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公开(公告)号：US10109358B2
公开(公告)日：2018-10-23
申请号：US15845310
申请日：2017-12-18
发明人： Noboru Shibata , Tomoharu Tanaka
摘要： Data storage circuits are connected to the bit lines in a one-to-one correspondence. A write circuit writes the data on a first page into a plurality of 5 first memory cells selected simultaneously by a word line. Thereafter, the write circuit writes the data on a second page into the plurality of first memory cell. Then, the write circuit writes the data on the first and second pages into second memory cells adjoining 10 the first memory cells in the bit line direction.
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公开(公告)号：US09881681B2
公开(公告)日：2018-01-30
申请号：US15251798
申请日：2016-08-30
发明人： Noboru Shibata , Tomoharu Tanaka
CPC分类号： G11C16/3427 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/12 , G11C16/3459 , G11C2211/5621 , G11C2211/5646 , G11C2211/5648 , G11C2216/14
摘要： Data storage circuits are connected to the bit lines in a one-to-one correspondence. A write circuit writes the data on a first page into a plurality of 5 first memory cells selected simultaneously by a word line. Thereafter, the write circuit writes the data on a second page into the plurality of first memory cell. Then, the write circuit writes the data on the first and second pages into second memory cells adjoining 10 the first memory cells in the bit line direction.
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公开(公告)号：US10699781B2
公开(公告)日：2020-06-30
申请号：US16539205
申请日：2019-08-13
发明人： Noboru Shibata , Tomoharu Tanaka
摘要： A memory cell array is configured to have a plurality of memory cells arranged in a matrix, each of the memory cells being connected to a word line and a bit line and being capable of storing n values (n is a natural number equal to or larger than 3). A control circuit controls the potentials of the word line and bit line according to input data and writes data into a memory cell. The control circuit writes data into the memory cell to a k-valued threshold voltage (k⇐n) in a write operation, precharges the bit line once, and then changes the potential of the word line an i number of times to verify whether the memory cell has reached an i-valued (i⇐k) threshold voltage.
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公开(公告)号：US20190362781A1
公开(公告)日：2019-11-28
申请号：US16539205
申请日：2019-08-13
发明人： Noboru Shibata , Tomoharu Tanaka
摘要： A memory cell array is configured to have a plurality of memory cells arranged in a matrix, each of the memory cells being connected to a word line and a bit line and being capable of storing n values (n is a natural number equal to or larger than 3). A control circuit controls the potentials of the word line and bit line according to input data and writes data into a memory cell. The control circuit writes data into the memory cell to a k-valued threshold voltage (k
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公开(公告)号：US10418117B2
公开(公告)日：2019-09-17
申请号：US16132208
申请日：2018-09-14
发明人： Noboru Shibata , Tomoharu Tanaka
摘要： Data storage circuits are connected to the bit lines in a one-to-one correspondence. A write circuit writes the data on a first page into a plurality of 5 first memory cells selected simultaneously by a word line. Thereafter, the write circuit writes the data on a second page into the plurality of first memory cell. Then, the write circuit writes the data on the first and second pages into second memory cells adjoining 10 the first memory cells in the bit line direction.
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公开(公告)号：US10096358B2
公开(公告)日：2018-10-09
申请号：US15832557
申请日：2017-12-05
发明人： Noboru Shibata , Tomoharu Tanaka
摘要： A memory cell array is configured to have a plurality of memory cells arranged in a matrix, each of the memory cells being connected to a word line and a bit line and being capable of storing n values (n is a natural number equal to or larger than 3). A control circuit controls the potentials of the word line and bit line according to input data and writes data into a memory cell. The control circuit writes data into the memory cell to a k-valued threshold voltage (k
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10.发明授权公开(公告)号：US10236058B2
公开(公告)日：2019-03-19
申请号：US15973644
申请日：2018-05-08
发明人： Tomoharu Tanaka , Jian Chen
IPC分类号： G11C16/04 , G11C11/56 , G11C16/12 , G11C16/34 , H01L27/115 , H01L27/11521 , H01L27/11524 , G11C16/10
摘要： A non-volatile semiconductor memory device includes an electrically data rewritable non-volatile semiconductor memory cell and a write circuit for writing data in the memory cell, the write circuit writing a data in the memory cells by supplying a write voltage Vpgm and a write control voltage VBL to the memory cell, continuing the writing of the data in the memory cell by changing the value of the write control voltage VBL in response to an advent of a first write state of the memory cell and inhibiting any operation of writing a data to the memory cell by further changing the value of the write control voltage VBL to Vdd in response to an advent of a second write state of the memory cell.
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