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1.发明申请公开(公告)号：US20190172530A1
公开(公告)日：2019-06-06
申请号：US16268726
申请日：2019-02-06
发明人： Tomoharu Tanaka , Jian Chen
IPC分类号： G11C11/56 , G11C16/34 , G11C16/10 , H01L27/11524 , H01L27/11521 , G11C16/04 , G11C16/12 , H01L27/115
摘要： A non-volatile semiconductor memory device includes an electrically data rewritable non-volatile semiconductor memory cell and a write circuit for writing data in the memory cell, the write circuit writing a data in the memory cells by supplying a write voltage Vpgm and a write control voltage VBL to the memory cell, continuing the writing of the data in the memory cell by changing the value of the write control voltage VBL in response to an advent of a first write state of the memory cell and inhibiting any operation of writing a data to the memory cell by further changing the value of the write control voltage VBL to Vdd in response to an advent of a second write state of the memory cell.
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2.发明申请公开(公告)号：US20200294582A1
公开(公告)日：2020-09-17
申请号：US16887306
申请日：2020-05-29
发明人： Tomoharu Tanaka , Jian Chen
IPC分类号： G11C11/56 , G11C16/04 , G11C16/34 , H01L27/115 , H01L27/11521 , H01L27/11524 , G11C16/12 , G11C16/10
摘要： A non-volatile semiconductor memory device includes an electrically data rewritable non-volatile semiconductor memory cell and a write circuit for writing data in the memory cell, the write circuit writing a data in the memory cells by supplying a write voltage Vpgm and a write control voltage VBL to the memory cell, continuing the writing of the data in the memory cell by changing the value of the write control voltage VBL in response to an advent of a first write state of the memory cell and inhibiting any operation of writing a data to the memory cell by further changing the value of the write control voltage VBL to Vdd in response to an advent of a second write state of the memory cell.
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公开(公告)号：US10706919B2
公开(公告)日：2020-07-07
申请号：US16268726
申请日：2019-02-06
发明人： Tomoharu Tanaka , Jian Chen
IPC分类号： G11C16/04 , G11C11/56 , G11C16/34 , H01L27/115 , H01L27/11521 , H01L27/11524 , G11C16/12 , G11C16/10
摘要： A non-volatile semiconductor memory device includes an electrically data rewritable non-volatile semiconductor memory cell and a write circuit for writing data in the memory cell, the write circuit writing a data in the memory cells by supplying a write voltage Vpgm and a write control voltage VBL to the memory cell, continuing the writing of the data in the memory cell by changing the value of the write control voltage VBL in response to an advent of a first write state of the memory cell and inhibiting any operation of writing a data to the memory cell by further changing the value of the write control voltage VBL to Vdd in response to an advent of a second write state of the memory cell.
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公开(公告)号：US10236058B2
公开(公告)日：2019-03-19
申请号：US15973644
申请日：2018-05-08
发明人： Tomoharu Tanaka , Jian Chen
IPC分类号： G11C16/04 , G11C11/56 , G11C16/12 , G11C16/34 , H01L27/115 , H01L27/11521 , H01L27/11524 , G11C16/10
摘要： A non-volatile semiconductor memory device includes an electrically data rewritable non-volatile semiconductor memory cell and a write circuit for writing data in the memory cell, the write circuit writing a data in the memory cells by supplying a write voltage Vpgm and a write control voltage VBL to the memory cell, continuing the writing of the data in the memory cell by changing the value of the write control voltage VBL in response to an advent of a first write state of the memory cell and inhibiting any operation of writing a data to the memory cell by further changing the value of the write control voltage VBL to Vdd in response to an advent of a second write state of the memory cell.
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公开(公告)号：US11183235B2
公开(公告)日：2021-11-23
申请号：US16887306
申请日：2020-05-29
发明人： Tomoharu Tanaka , Jian Chen
IPC分类号： G11C16/04 , G11C11/56 , G11C16/34 , H01L27/115 , H01L27/11521 , H01L27/11524 , G11C16/12 , G11C16/10
摘要： A non-volatile semiconductor memory device includes an electrically data rewritable non-volatile semiconductor memory cell and a write circuit for writing data in the memory cell, the write circuit writing a data in the memory cells by supplying a write voltage Vpgm and a write control voltage VBL to the memory cell, continuing the writing of the data in the memory cell by changing the value of the write control voltage VBL in response to an advent of a first write state of the memory cell and inhibiting any operation of writing a data to the memory cell by further changing the value of the write control voltage VBL to Vdd in response to an advent of a second write state of the memory cell.
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公开(公告)号：US09734899B2
公开(公告)日：2017-08-15
申请号：US15299255
申请日：2016-10-20
发明人： Tomoharu Tanaka , Jian Chen
IPC分类号： G11C7/10 , G11C11/56 , G11C16/04 , G11C16/12 , G11C16/34 , H01L27/115 , H01L27/11521 , H01L27/11524 , G11C16/10
CPC分类号： G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/12 , G11C16/34 , G11C16/3418 , G11C16/3427 , G11C16/3459 , G11C16/3481 , G11C2211/5621 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A non-volatile semiconductor memory device includes an electrically data rewritable non-volatile semiconductor memory cell and a write circuit for writing data in the memory cell, the write circuit writing a data in the memory cells by supplying a write voltage Vpgm and a write control voltage VBL to the memory cell, continuing the writing of the data in the memory cell by changing the value of the write control voltage VBL in response to an advent of a first write state of the memory cell and inhibiting any operation of writing a data to the memory cell by further changing the value of the write control voltage VBL to Vdd in response to an advent of a second write state of the memory cell.
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公开(公告)号：US20220229588A1
公开(公告)日：2022-07-21
申请号：US17149867
申请日：2021-01-15
发明人： Deepanshu Dutta , James Kai , Johann Alsmeier , Jian Chen
IPC分类号： G06F3/06 , G11C16/04 , G11C16/26 , G11C16/10 , H01L27/11582
摘要： An integrated memory assembly comprises a memory die and a control die bonded to the memory die. The memory die comprises a three dimensional non-volatile memory structure and a first plurality of sense amplifiers. The first plurality of sense amplifiers are connected to the memory structure and are positioned on a substrate of the memory die between the memory structure and the substrate such that the memory structure is directly above the first plurality of sense amplifiers. The control die comprises a second plurality of sense amplifiers that are connected to the memory structure. The first plurality of sense amplifiers and the second plurality of sense amplifiers are configured to be used to concurrently perform memory operations.
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8.发明申请公开(公告)号：US20200295029A1
公开(公告)日：2020-09-17
申请号：US16889030
申请日：2020-06-01
发明人： Jixin Yu , Tae-Kyung Kim , Johann Alsmeier , Yan Li , Jian Chen
IPC分类号： H01L27/11578 , G11C5/02 , G11C5/06
摘要： Three-dimensional memory devices in the form of a memory die includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and memory stack structures extending through the alternating stack, in which each of the memory stack structures includes a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film. Bit lines are electrically connected to an end portion of a respective one of the vertical semiconductor channels. Bump connection via structures contact a top surface of a respective one of the bit lines, in which each of the bump connection via structures has a greater lateral dimension along a lengthwise direction of the bit lines than along a widthwise direction of the bit lines. Metallic bump structures of another semiconductor die contact respective ones of the bump connection via structures to make respective electrical connections between the two dies.
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9.发明申请公开(公告)号：US20180261283A1
公开(公告)日：2018-09-13
申请号：US15973644
申请日：2018-05-08
发明人： Tomoharu Tanaka , Jian Chen
IPC分类号： G11C11/56 , H01L27/11524 , H01L27/11521 , H01L27/115 , G11C16/34 , G11C16/12 , G11C16/10 , G11C16/04
CPC分类号： G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/12 , G11C16/34 , G11C16/3418 , G11C16/3427 , G11C16/3459 , G11C16/3481 , G11C2211/5621 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A non-volatile semiconductor memory device includes an electrically data rewritable non-volatile semiconductor memory cell and a write circuit for writing data in the memory cell, the write circuit writing a data in the memory cells by supplying a write voltage Vpgm and a write control voltage VBL to the memory cell, continuing the writing of the data in the memory cell by changing the value of the write control voltage VBL in response to an advent of a first write state of the memory cell and inhibiting any operation of writing a data to the memory cell by further changing the value of the write control voltage VBL to Vdd in response to an advent of a second write state of the memory cell.
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公开(公告)号：US10043558B2
公开(公告)日：2018-08-07
申请号：US15628417
申请日：2017-06-20
发明人： Grishma Shah , Yan Li , Jian Chen , Kenneth Louie , Nian Niles Yang
CPC分类号： G11C7/1009 , G11C7/1015 , G11C7/1039 , G11C7/1063 , G11C11/56 , G11C11/5642 , G11C16/0483 , G11C16/26 , G11C2211/563 , G11C2216/20
摘要： Read operations are performed in a multi-plane memory device. A state machine interfaces an external controller to each plane of memory cells to allow reading from selected word lines in the planes. In one approach, different types of read operations are performed in different planes, such as a multi-level cell read, e.g., a lower, middle or upper page read and a single-level cell (SLC) read. When the read operation in one plane uses fewer read voltages than another plane, the read data can be output early from the one plane while read operations continue on the other plane. The external controller can also command a cache release for one plane after outputting data from the caches of another plane. Read voltages can be set for each plane in a respective set of registers.
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