公开(公告)号：US20200294811A1

公开(公告)日：2020-09-17

申请号：US16561909

申请日：2019-09-05

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Yuya MATSUBARA ,  Hiroshi Kubota

IPC: H01L21/311 ,  H01L27/11582 ,  H01L21/28

Abstract: In one embodiment, a method of manufacturing a semiconductor device includes forming a stacked film on a substrate. The method further includes forming, on the stacked film, a mask layer formed of a tungsten compound and including impurity atoms having a concentration of 1.0×1020 atoms/cm3 or more. The method further includes etching the stacked film using the mask layer as an etching mask.

公开(公告)号：US20200090931A1

公开(公告)日：2020-03-19

申请号：US16283609

申请日：2019-02-22

Applicant: Toshiba Memory Corporation

Inventor： Yuya MATSUBARA ,  Masayuki Kitamura ,  Atsuko Sakata

IPC: H01L21/02 ,  H01L21/285 ,  C23C16/50 ,  C23C16/30 ,  C23C16/52 ,  C23C16/32

Abstract: A substrate processing apparatus includes a chamber to accommodate a substrate. The apparatus includes a stage to support the substrate in the chamber. The apparatus includes an electrode disposed above the stage and containing aluminum. The electrode generates plasma from gas supplied into the chamber to form a first film on the substrate by the plasma. The apparatus further includes a second film formed on a surface of the electrode and containing aluminum and fluorine or containing aluminum and oxygen.

公开(公告)号：US20180145251A1

公开(公告)日：2018-05-24

申请号：US15704802

申请日：2017-09-14

Applicant: Toshiba Memory Corporation

Inventor： Hiromichi KURIYAMA ,  Yuya MATSUBARA ,  Kazunori HARADA ,  Takuya HIROHASHI ,  Harumi SEKI ,  Masumi SAITOH

IPC: H01L45/00 ,  G11C13/00

CPC classification number: H01L45/10 ,  G11C13/0011 ,  G11C13/004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0045 ,  G11C2013/0078 ,  G11C2213/33 ,  G11C2213/34 ,  G11C2213/52 ,  G11C2213/56 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146

Abstract: According to one embodiment, a variable resistance element includes first and second conductive layers and a first layer. The first conductive layer includes at least one of silver, copper, zinc, titanium, vanadium, chrome, manganese, iron, cobalt, nickel, tellurium, or bismuth. The second conductive layer includes at least one of platinum, gold, iridium, tungsten, palladium, rhodium, titanium nitride, or silicon. The first layer includes oxygen and silicon and is provided between the first conductive layer and the second conductive layer. The first layer includes a plurality of holes. The holes are smaller than a thickness of the first layer along a first direction. The first direction is from the second conductive layer toward the first conductive layer. The first layer does not include carbon, or a composition ratio of carbon included in the first layer to silicon included in the first layer is less than 0.1.

公开(公告)号：US20200075341A1

公开(公告)日：2020-03-05

申请号：US16283570

申请日：2019-02-22

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Yuya MATSUBARA ,  Masayuki KITAMURA ,  Atsuko SAKATA

IPC: H01L21/3065 ,  H01L21/311 ,  H01L27/11582

Abstract: A mask member contains tungsten (W), boron (B), and carbon (C). The mask member includes a first portion in contact with a process film, the first portion, in which the terms of the composition ratio, which correspond to boron and carbon, are larger than the term of the composition ratio, which corresponds to tungsten, and a second portion in which the term of the composition ratio, which corresponds to tungsten, is larger than the terms of the composition ratio, which correspond to carbon and boron.