公开(公告)号：US20200303308A1

公开(公告)日：2020-09-24

申请号：US16559001

申请日：2019-09-03

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Masayuki KITAMURA ,  Atsushi KATO

IPC: H01L23/532 ,  H01L23/522 ,  H01L21/768

Abstract: According to one embodiment, a semiconductor device includes: a semiconductor substrate; a first via provided on the semiconductor substrate; a metal wiring provided on the first via; and a second via provided on the metal wiring. One of the side surfaces facing each other in the first direction of the metal wiring and one of the side surfaces facing each other in the first direction of the second via are aligned in the first direction.

公开(公告)号：US20200091088A1

公开(公告)日：2020-03-19

申请号：US16294984

申请日：2019-03-07

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Satoshi WAKATSUKI ,  Masayuki KITAMURA ,  Atsuko SAKATA

IPC: H01L23/00 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/06

Abstract: In one embodiment, a semiconductor device includes a substrate, and a plurality of insulating layers provided on the substrate. The device further includes a plurality of electrode layers provided on the substrate alternately with the plurality of insulating layers and including metal atoms and impurity atoms different from the metal atoms, lattice spacing between the metal atoms in the electrode layers being greater than lattice spacing between the metal atoms in an elemental substance of the metal atoms.

公开(公告)号：US20210233872A1

公开(公告)日：2021-07-29

申请号：US17231350

申请日：2021-04-15

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Satoshi WAKATSUKI ,  Masayuki KITAMURA ,  Atsuko SAKATA

IPC: H01L23/00 ,  H01L29/06 ,  H01L27/11568 ,  H01L27/11521

Abstract: In one embodiment, a semiconductor device includes a substrate, and a plurality of insulating layers provided on the substrate. The device further includes a plurality of electrode layers provided on the substrate alternately with the plurality of insulating layers and including metal atoms and impurity atoms different from the metal atoms, lattice spacing between the metal atoms in the electrode layers being greater than lattice spacing between the metal atoms in an elemental substance of the metal atoms.

公开(公告)号：US20200258722A1

公开(公告)日：2020-08-13

申请号：US16553982

申请日：2019-08-28

Applicant: Toshiba Memory Corporation

Inventor： Katsuaki NATORI ,  Hiroshi TOYODA ,  Masayuki KITAMURA ,  Takayuki BEPPU

IPC: H01J37/32 ,  H01L21/285 ,  H01L27/11582 ,  H01L21/673 ,  H01L21/28 ,  C23C16/455 ,  C23C16/06 ,  C23C16/44 ,  C23C16/458

Abstract: A method of manufacturing a semiconductor device includes placing a substrate in a housing, supplying first gas containing molybdenum to the housing to form a film that contains molybdenum, on the substrate, removing the substrate with the formed film from the hosing, and then supplying second gas containing chlorine to the housing to remove molybdenum deposited on a surface of the housing.

公开(公告)号：US20180082893A1

公开(公告)日：2018-03-22

申请号：US15449233

申请日：2017-03-03

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Fuyuma ITO ,  Yasuhito YOSHIMIZU ,  Yuya AKEBOSHI ,  Hisashi OKUCHI ,  Masayuki KITAMURA

IPC: H01L21/768 ,  H01L21/027 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76879 ,  H01L21/0272 ,  H01L21/0273 ,  H01L21/76802 ,  H01L21/76831 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53238

Abstract: According to some embodiments, a semiconductor device manufacturing method includes forming a sacrificial film on a material film. The method includes processing the sacrificial film, and forming a first groove in the sacrificial film having a first width and a second groove in the sacrificial film having a second width larger than the first width, the material film defining a base of the first groove and a base of the second groove. The method includes forming a catalyst layer on the sacrificial film, and on the base of the first groove and the base of the second groove. The method includes forming a first metal film having a thickness equal to or larger than half the first width and smaller than half the second width on the catalyst layer by plating. The method includes removing at least a portion of the first metal film in the second groove while leaving a portion of the first metal film in the first groove unremoved. The method includes removing the catalyst layer on the sacrificial film while leaving the catalyst layer on the base of the second groove unremoved. The method includes forming a second metal film in the second groove by the plating.

公开(公告)号：US20200075341A1

公开(公告)日：2020-03-05

申请号：US16283570

申请日：2019-02-22

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Yuya MATSUBARA ,  Masayuki KITAMURA ,  Atsuko SAKATA

IPC: H01L21/3065 ,  H01L21/311 ,  H01L27/11582

Abstract: A mask member contains tungsten (W), boron (B), and carbon (C). The mask member includes a first portion in contact with a process film, the first portion, in which the terms of the composition ratio, which correspond to boron and carbon, are larger than the term of the composition ratio, which corresponds to tungsten, and a second portion in which the term of the composition ratio, which corresponds to tungsten, is larger than the terms of the composition ratio, which correspond to carbon and boron.

公开(公告)号：US20180274092A1

公开(公告)日：2018-09-27

申请号：US15695929

申请日：2017-09-05

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Masayuki KITAMURA ,  Atsuko SAKATA ,  Satoshi WAKATSUKI

IPC: C23C16/44 ,  H01L21/285 ,  C23C16/455 ,  C23C16/458 ,  H01L21/205 ,  C30B29/06

CPC classification number: C23C16/4401 ,  C23C16/4412 ,  C23C16/45527 ,  C23C16/45565 ,  C23C16/4587 ,  C30B29/06 ,  H01L21/205 ,  H01L21/28556 ,  H01L21/76877

Abstract: A semiconductor manufacturing apparatus includes a reaction chamber configured to perform a process on a semiconductor substrate using a gas mixture comprising a first gas, and a first path configured to exhaust resultant gas that comprises the first gas from the reaction chamber. The semiconductor manufacturing apparatus further includes a first trap provided in the first path and configured to extract at least a portion of the first gas from the resultant gas, and a second path in which the trap is not provided and configured to exhaust the resultant gas from the reaction chamber.

公开(公告)号：US20190259621A1

公开(公告)日：2019-08-22

申请号：US16031544

申请日：2018-07-10

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Katsuaki NATORI ,  Satoshi WAKATSUKI ,  Masayuki KITAMURA

IPC: H01L21/285 ,  H01L21/768

Abstract: A production method of a semiconductor device includes introducing a reduction gas for reducing metal to a space containing a target to be used as the semiconductor device. The method also includes introducing a material gas and a first gas simultaneously to the space on a basis of a predetermined partial pressure ratio after introducing the reduction gas, to form a film that contains the metal, on the target. The material gas etches the metal when only the material gas is flowed. The first gas is different from the material gas. The predetermined partial pressure ratio is a ratio of the material gas and the first gas.

公开(公告)号：US20180261624A1

公开(公告)日：2018-09-13

申请号：US15688646

申请日：2017-08-28

Applicant: Toshiba Memory Corporation

Inventor： Taishi ISHIKURA ,  Atsunobu ISOBAYASHI ,  Masayuki KITAMURA ,  Akihiro KAJITA

IPC: H01L27/11582 ,  H01L27/11568

CPC classification number: H01L27/11582 ,  H01L27/11551 ,  H01L27/11553 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11578 ,  H01L29/66833 ,  H01L29/7926 ,  H01L45/00

Abstract: A semiconductor device includes an under layer, a stacked body comprising a plurality of conductive layers and insulating layers alternately stacked one over the other in a stacking direction, above the insulating layer, a columnar portion extending into the stacked body in the stacking direction of the stacked body, and a graphene film between at least one of the conductive layers and adjacent insulating layers and between the at least one of the conductive layers and the columnar portion.

公开(公告)号：US20200294793A1

公开(公告)日：2020-09-17

申请号：US16567269

申请日：2019-09-11

Applicant: Toshiba Memory Corporation

Inventor： Masayuki KITAMURA ,  Takayuki BEPPU ,  Tomotaka ARIGA

IPC: H01L21/02 ,  C23C16/44 ,  C23C16/455 ,  C23C16/14 ,  H01L21/306 ,  H01L21/285 ,  H01L21/67

Abstract: In a manufacturing method of a semiconductor device according to one embodiment, a first gas containing a first metal element is introduced into a chamber having a substrate housed therein. Next, the first gas is discharged from the chamber using a purge gas. Subsequently, a second gas reducing the first gas is introduced into the chamber. Next, the second gas is discharged from the chamber using the purge gas. Further, a third gas different from the first gas, the second gas, and the purge gas is introduced into the chamber at least either at a time of discharging the first gas or at a time of discharging the second gas.