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    Dynamic content addressable memory device and a method of operating thereof
    1.
    发明授权
    Dynamic content addressable memory device and a method of operating thereof 失效
    动态内容可寻址存储器件及其操作方法

    公开(公告)号：US5319589A

    公开(公告)日：1994-06-07

    申请号：US966921

    申请日：1992-10-27

    申请人： Tadato Yamagata ,  Masaaki Mihara ,  Takeshi Hamamoto ,  Hideyuki Ozaki

    发明人： Tadato Yamagata ,  Masaaki Mihara ,  Takeshi Hamamoto ,  Hideyuki Ozaki

    IPC分类号： G11C15/00 ,  G11C11/4094 ,  G11C15/04 ,  G11C29/04

    CPC分类号： G11C11/4094 ,  G11C15/043

    摘要： A bit line control circuit is disclosed for implementing a dynamic content addressable memory. The bit line control circuit includes a read circuit 12 and a first write circuit 13 connected to data line pairs DT, /DT, a sense amplifier 14, a bit line discharge circuit 15, a bit line charge circuit 16, a transfer gate circuit 17, and a second write circuit 18. The bit line control circuit is connected to a CAM cell array through bit lines BLa, /BLa. Various operations such as write, read, refresh and match detection and the like necessary in the dynamic associative memory can be implemented under simple timing control by a simple circuit configuration.

    摘要翻译： 公开了一种用于实现动态内容可寻址存储器的位线控制电路。 位线控制电路包括读取电路12和连接到数据线对DT，/ DT的第一写入电路13，读出放大器14，位线放电电路15，位线充电电路16，传输门电路17 和第二写入电路18.位线控制电路通过位线BLa，/ BLa连接到CAM单元阵列。 可以通过简单的电路配置在简单的定时控制下，在动态关联存储器中所需的诸如写入，读取，刷新和匹配检测等各种操作。

    Content addressable semiconductor memory device and operating method therefor
    2.
    发明授权
    Content addressable semiconductor memory device and operating method therefor 失效
    内容可寻址半导体存储器件及其操作方法

    公开(公告)号：US5126968A

    公开(公告)日：1992-06-30

    申请号：US605707

    申请日：1990-10-30

    申请人： Takeshi Hamamoto ,  Toshifumi Kobayashi ,  Tadato Yamagata ,  Masaaki Mihara

    发明人： Takeshi Hamamoto ,  Toshifumi Kobayashi ,  Tadato Yamagata ,  Masaaki Mihara

    IPC分类号： G11C15/04

    CPC分类号： G11C15/043 ,  G11C15/04

    摘要： A semiconductor memory device comprises a plurality or CAM cells. In a refreshing operation, data of "1" is applied to all of bit lines and inversion bit lines. In the CAM cells storing the data "1", writing of the data "1" onto the bit lines and the inversion bit lines is performed. Then, the data of "0" is applied to all of the bit lines and the inversion bit lines. In the CAM cells storing the data "0", writing of the data "0" onto the bit lines and the inversion bit lines is performed. In a partial writing operation, in the CAM cells to which writing is performed, a first control node is activated, thereby making it possible to write the CAM cells. In the rest of the CAM cells, the first control node is inactivated, thereby making it impossible to write the CAM cells.

    摘要翻译： 半导体存储器件包括多个或多个单元。 在刷新操作中，将数据“1”应用于所有位线和反转位线。 在存储数据“1”的CAM单元中，执行数据“1”到位线和反转位线的写入。 然后，将数据“0”应用于所有的位线和反转位线。 在存储数据“0”的CAM单元中，执行数据“0”到位线和反转位线的写入。 在部分写入操作中，在执行写入的CAM单元中，第一控制节点被激活，从而使得可以写入CAM单元。 在其余的CAM单元中，第一控制节点被去激活，从而不可能写入CAM单元。

    Circuit for prioritizing outputs of an associative memory with parallel inhibition paths and a compact architecture
    3.
    发明授权
    Circuit for prioritizing outputs of an associative memory with parallel inhibition paths and a compact architecture 失效
    用于对具有并行抑制路径和紧凑架构的关联存储器的输出进行优先级排列的电路

    公开(公告)号：US5418923A

    公开(公告)日：1995-05-23

    申请号：US937763

    申请日：1992-09-01

    申请人： Masaaki Mihara ,  Tadato Yamagata ,  Takeshi Hamamoto

    发明人： Masaaki Mihara ,  Tadato Yamagata ,  Takeshi Hamamoto

    IPC分类号： G11C15/04 ,  G11C15/00

    CPC分类号： G11C15/04

    摘要： An encoding circuit shortens time required for a coincidence signal to be converted into an address code after selected and output sequentially according to a predetermined priority level when the coincidence signal is obtained from an associative memory. The circuit is provided with a contention arbitrating circuit for a lower subgroup and a contention arbitrating circuit for a higher subgroup. In the contention arbitrating circuit for a lower subgroup and the contention arbitrating circuit for higher subgroup, each coincidence signal simultaneously activates inhibiting signals whose priority levels are lower than the priority level of the coincidence signal. A lower half of coincidence signals are arranged in descending order in the contention arbitrating circuit for a lower subgroup and a higher half of coincidence signals are arranged in ascending order in the contention arbitrating circuit for a higher subgroup. The contention arbitrating circuit for a lower subgroup and the contention arbitrating circuit for a higher subgroup are arranged in a triangular array and a complementary triangular array, respectively.

    摘要翻译： 当从联想存储器获得符合信号时，编码电路将一致信号所需的时间缩短为根据预定的优先级依次选择和输出之后被转换成地址码。 该电路设置有用于较低子组的竞争仲裁电路和用于较高子组的争用仲裁电路。 在用于较低子组的竞争仲裁电路和较高子组的竞争仲裁电路中，每个符合信号同时激活优先级低于一致信号的优先级的禁止信号。 在下一个子组的竞争仲裁电路中，按照降序排列下半部分的符合信号，并且在较高子组的竞争仲裁电路中按照升序排列较高的一半符号信号。 用于较低子组的争用仲裁电路和用于较高子组的争用仲裁电路分别以三角阵列和互补三角阵列排列。

    Content addressable memory device and a method of disabling a coincidence word thereof
    4.
    发明授权
    Content addressable memory device and a method of disabling a coincidence word thereof 失效
    内容可寻址存储装置和禁止其重合字的方法

    公开(公告)号：US5388066A

    公开(公告)日：1995-02-07

    申请号：US084098

    申请日：1993-07-01

    申请人： Takeshi Hamamoto ,  Tadato Yamagata ,  Masaaki Mihara

    发明人： Takeshi Hamamoto ,  Tadato Yamagata ,  Masaaki Mihara

    IPC分类号： G06F17/30 ,  G11C15/00 ,  G11C15/04

    CPC分类号： G06F17/30982 ,  G11C15/00 ,  G11C15/04 ,  G11C15/043

    摘要： A data storing circuit including memory cells arranged in a plurality of rows and columns and flag cells corresponding to respective rows for storing flag information, the memory cells and the flag cell of the same row constituting one word, is provided. When a retrieval data is externally applied, the data included in the retrieval data is compared with the data of the memory cell, and the flag information stored in the retrieval data is compared with the flag stored in the flag cell. Respective results of comparison are output to a match line. Logical operation circuit carries out logical operation dependent on the result of comparison output to the match line, and writes the logical output to the flag cell of the data storing circuit.

    摘要翻译： 一种数据存储电路，其特征在于，具备排列成多个行和列的存储单元以及对应于各行的标志单元，用于存储标志信息，存储单元和构成一个字的同一行的标志单元。 当外部应用检索数据时，将包括在检索数据中的数据与存储单元的数据进行比较，并将存储在检索数据中的标志信息与存储在标志单元中的标志进行比较。 比较结果输出到匹配行。 逻辑运算电路根据比较结果输出到匹配线进行逻辑运算，并将逻辑输出写入数据存储电路的标志单元。

    Semiconductor integrated circuit device having improved stacked capacitor and manufacturing method therefor
    5.
    发明授权
    Semiconductor integrated circuit device having improved stacked capacitor and manufacturing method therefor 失效
    具有改进的堆叠电容器的半导体集成电路器件及其制造方法

    公开(公告)号：US5146300A

    公开(公告)日：1992-09-08

    申请号：US830971

    申请日：1992-02-10

    申请人： Takeshi Hamamoto ,  Toshifumi Kobayashi ,  Tadato Yamagata ,  Masaaki Mihara

    发明人： Takeshi Hamamoto ,  Toshifumi Kobayashi ,  Tadato Yamagata ,  Masaaki Mihara

    IPC分类号： G11C15/04 ,  H01L27/108

    CPC分类号： H01L27/108 ,  G11C15/043

    摘要： A semiconductor integrated circuit device including a semiconductor substrate having a main surface; a first conductive region formed on the main surface; a second conductive region formed on the main surface, spaced apart from the first conductive region and to be electrically connected to the first conductive region; and a capacitor having a storage node connecting the first and second conductive regions. The storage node serves to connect the first and second conductive regions and simultaneously stores charges. In other aspects of the invention, there are provided a memory cell having a structure described above, and a method of manufacturing the above-described semiconductor integrated circuit device.

    摘要翻译： 一种半导体集成电路器件，包括：具有主表面的半导体衬底; 形成在所述主表面上的第一导电区域; 形成在所述主表面上的第二导电区域，与所述第一导电区域间隔开并且电连接到所述第一导电区域; 以及具有连接第一和第二导电区域的存储节点的电容器。 存储节点用于连接第一和第二导电区域并同时存储电荷。 在本发明的其他方面，提供了一种具有上述结构的存储单元，以及制造上述半导体集成电路器件的方法。

    Memory module
    6.
    发明授权
    Memory module 失效
    内存模块

    公开(公告)号：US06515922B1

    公开(公告)日：2003-02-04

    申请号：US09621693

    申请日：2000-07-21

    申请人： Tadato Yamagata

    发明人： Tadato Yamagata

    IPC分类号： G11C700

    CPC分类号： G11C29/40

    摘要： A memory module is provided with switch groups (SD0a to SD7a) in corresponding relation to data lines (DQ0 to DQ63) connected to memory devices (MD0 to MD7). The switch groups (SD0a to SD7a) connect all of the data lines (DQ0 to DQ63) to a portion external to the memory module (MMa) in a memory operation, and connect all of the data lines (DQ0 to DQ63) to inputs of an exclusive NOR circuit (EXa) after common 1-bit data is written into the memory devices (MD0 to MD7) in a testing operation. A malfunction of the memory devices (MD0 to MD7) is detected using an output signal (TMSa) from the exclusive NOR circuit (EXa). The memory module is accomplished which allows an inexpensive tester to conduct an electrical assembly check and a simple data write and read operation test upon the memory devices, which includes a small number of I/O pins for the check and test, and which does not deteriorate data input/output characteristics of the memory devices.

    摘要翻译： 存储器模块具有与连接到存储器件（MD0至MD7）的数据线（DQ0至DQ63）对应关系的开关组（SD0a至SD7a）。 开关组（SD0a〜SD7a）在存储器动作中将所有数据线（DQ0〜DQ63）连接到存储器模块外部的一部分（MMa），并将所有数据线（DQ0〜DQ63）连接到 在测试操作中，将公共1位数据写入存储器件（MD0至MD7）之后的异或电路（EXa）。 使用来自异或电路（EXa）的输出信号（TMSa）来检测存储器件（MD0至MD7）的故障。 完成了内存模块，允许廉价的测试人员对存储设备进行电气组装检查和简单的数据写入和读取操作测试，存储器件包括少量用于检查和测试的I / O引脚，不存在 恶化了存储器件的数据输入/输出特性。

    Fast memory device allowing suppression of peak value of operational current
    8.
    发明授权
    Fast memory device allowing suppression of peak value of operational current 失效
    快速存储器件允许抑制工作电流的峰值

    公开(公告)号：US5726943A

    公开(公告)日：1998-03-10

    申请号：US583810

    申请日：1996-01-05

    申请人： Tadato Yamagata ,  Kazutami Arimoto

    发明人： Tadato Yamagata ,  Kazutami Arimoto

    IPC分类号： G11C7/06 ,  G11C11/406 ,  G11C11/409 ,  G11C11/4091 ,  G11C7/00 ,  G11C7/02 ,  G11C8/00

    CPC分类号： G11C11/4091 ,  G11C11/406 ,  G11C7/065

    摘要： A memory cell array of a dynamic semiconductor memory device is divided into a plurality of memory cell blocks. A block selecting circuit selects and refreshes larger number of memory cell blocks in refreshing mode than the number of those selected during normal mode. Sense amplifiers in the memory cell blocks selected by the block selecting circuit are selectively driven with smaller driving force in refreshing mode than that in normal mode. More preferably the driving force is changed during the amplifying operation so as to achieve both the high sensitivity and the suppression of the peak value of the operational current.

    摘要翻译： 动态半导体存储器件的存储单元阵列被分成多个存储单元块。 块选择电路在更新模式下选择和刷新大量的在正常模式下选择的存储单元块的数量。 通过块选择电路选择的存储单元块中的感测放大器在刷新模式下以比正常模式更小的驱动力被选择性地驱动。 更优选地，在放大操作期间驱动力被改变，以便实现操作电流的峰值的高灵敏度和抑制。

    Test circuit of semiconductor memory device
    10.
    发明授权
    Test circuit of semiconductor memory device 失效
    半导体存储器件的测试电路

    公开(公告)号：US5228000A

    公开(公告)日：1993-07-13

    申请号：US733028

    申请日：1991-07-22

    申请人： Tadato Yamagata

    发明人： Tadato Yamagata

    IPC分类号： G11C29/28 ,  G11C29/32

    CPC分类号： G11C29/28 ,  G11C29/32

    摘要： In a test mode, bit information of the same logic is written into a corresponding memory cell of each of subarray 5a-5d. Bit information written in respective memory cells is simultaneously read and supplied to exclusive-OR gates 12a-12d. Each of exclusive-OR gates logics of read bit information and an expected value data supplied as an input to an external input pin D.sub.IN to supply the test determination result as an output. The outputs of respective exclusive-OR gates 12a-12d are serially supplied, through transistors 18a-18d which are sequentially and selectively turned on by a shift register 15, to an external output pin D.sub.OUT.

    摘要翻译： 在测试模式中，将相同逻辑的位信息写入子阵列5a-5d的相应存储单元。 写入各个存储单元的位信息被同时读取并提供给异或门12a-12d。 读取位信息的异或门逻辑和作为输入提供给外部输入引脚DIN的期望值数据，以将测试确定结果作为输出。 通过由移位寄存器15依次选择性地导通的晶体管18a-18d向外部输出引脚DOUT串联提供各异或门12a-12d的输出。