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30 条记录 (耗时 0.022 秒)

    Interface circuit
    3.
    发明授权
    Interface circuit 失效
    接口电路

    公开(公告)号：US07724606B2

    公开(公告)日：2010-05-25

    申请号：US11882117

    申请日：2007-07-30

    申请人： Tokuya Osawa ,  Masaru Haraguchi ,  Yoshikazu Morooka ,  Hiroshi Kinoshita

    发明人： Tokuya Osawa ,  Masaru Haraguchi ,  Yoshikazu Morooka ,  Hiroshi Kinoshita

    IPC分类号： G11C8/00

    CPC分类号： G11C8/08 ,  G11C7/1066

    摘要： A variable delay line receives and delays a data strobe signal transferred from a data source side in synchronization with a transfer data by a predetermined period, and produces a delayed data strobe signal and the non-delayed data strobe signal to a detector. The detector determines that a preamble period ends and effective data is transferred, when the delayed data strobe signal is at the L level at the time of rising of the non-delayed data strobe signal from the L level to the H level. According to a result of detection, an interface circuit unit takes in the transfer data and initializes a take-in address. The data strobe signal changes to a high-impedance state when a postamble ends. An influence of a glitch noise is avoided upon this change of the data strobe signal, and the data transfer can be executed fast and accurately.

    摘要翻译： 可变延迟线接收并延迟从数据源侧与传送数据同步预定周期的数据选通信号，并将延迟数据选通信号和非延迟数据选通信号提供给检测器。 当非延迟数据选通信号从L电平上升到H电平时，当延迟的数据选通信号为L电平时，检测器确定前导码周期结束并传送有效数据。 根据检测结果，接口电路单元接收传送数据并初始化接收地址。 当后同步码结束时，数据选通信号变为高阻态。 数据选通信号的变化可以避免毛刺噪声的影响，可以快速准确地执行数据传送。

    Semiconductor memory device having high data input/output frequency and capable of efficiently testing circuit associated with data input/output
    4.
    发明授权
    Semiconductor memory device having high data input/output frequency and capable of efficiently testing circuit associated with data input/output 失效
    具有高数据输入/输出频率并能够有效测试与数据输入/输出相关的电路的半导体存储器件

    公开(公告)号：US06421291B1

    公开(公告)日：2002-07-16

    申请号：US09510532

    申请日：2000-02-22

    申请人： Naoya Watanabe ,  Yoshikazu Morooka

    发明人： Naoya Watanabe ,  Yoshikazu Morooka

    IPC分类号： G11C700

    CPC分类号： G11C7/222 ,  G11C7/1006 ,  G11C29/02

    摘要： A data input/output circuit includes an S/P data conversion circuit which converts serial data input to a data terminal into a parallel data and transmits the parallel data to write data lines, a P/S data conversion circuit which converts parallel data on read data lines to serial data and outputs the serial data to the data terminal, and an input/output test circuit placed between the write data lines and the read data lines. The input/output test circuit responds to an input/output test signal to directly transfer data on the write data lines respectively to the read data lines without passing them through a memory cell array.

    摘要翻译： 数据输入/输出电路包括将输入到数据终端的串行数据转换为并行数据并将并行数据发送到写入数据线的S / P数据转换电路，将读取的并行数据转换成P / S数据转换电路 数据线连接到串行数据，并将串行数据输出到数据终端，以及输入/输出测试电路，位于写数据线和读数据线之间。 输入/输出测试电路响应于输入/输出测试信号，以将数据线上的数据直接传送到读取的数据线，而不会将它们通过存储单元阵列。

    Redundancy circuit for repairing defective bits in semiconductor memory device
    5.
    发明授权
    Redundancy circuit for repairing defective bits in semiconductor memory device 失效
    用于修复半导体存储器件中的有缺陷的位的冗余电路

    公开(公告)号：US5574729A

    公开(公告)日：1996-11-12

    申请号：US338817

    申请日：1994-11-10

    申请人： Mitsuya Kinoshita ,  Shigeru Mori ,  Yoshikazu Morooka ,  Hiroshi Miyamoto ,  Shigeru Kikuda ,  Makoto Suwa

    发明人： Mitsuya Kinoshita ,  Shigeru Mori ,  Yoshikazu Morooka ,  Hiroshi Miyamoto ,  Shigeru Kikuda ,  Makoto Suwa

    IPC分类号： G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  G06F11/00

    CPC分类号： G11C29/848

    摘要： A semiconductor memory device includes a plurality of memory blocks, i main row or column select lines extending over the plurality of memory blocks, and a decoder for selecting one of the main row or column select lines in accordance with an applied address signal. The decoder includes i outputs. Each of the memory blocks includes a plurality of memory cells arranged in rows and columns and at least (i+1) sub row or column select lines each for selecting one row or one column of memory cells. A shift redundancy circuit is provided for each of the memory blocks, for connecting the main row or column select line and the sub row or column select line. The shift redundancy circuit includes a switch circuit for connecting one main row or column select line to one of the plurality of adjacent sub row or column select lines, and a circuit for setting a connection path of the switch circuit. The shift redundancy circuit connects successively adjacent sub row or column select lines to main row or column select lines in one to one correspondence except a defective sub row or column select line associated with a defective bit.

    摘要翻译： 一种半导体存储器件包括多个存储块，i个在多个存储块上延伸的主行或列选择线，以及用于根据所施加的地址信号选择主行或列选择线中的一个的解码器。 解码器包括i个输出。 每个存储块包括排列成行和列的多个存储器单元和至少（i + 1）个子行或列选择线，每个用于选择一行或一列存储单元。 为每个存储块提供移位冗余电路，用于连接主行或列选择线和子行或列选择线。 移位冗余电路包括用于将一个主行或列选择线连接到多个相邻子行或列选择线中的一个的开关电路和用于设置开关电路的连接路径的电路。 除了与有缺陷的位相关联的有缺陷的子行或列选择线之外，移位冗余电路将连续相邻的子行或列选择线以一对一的对应方式连接到主行或列选择线。

    INTERFACE CIRCUIT
    6.
    发明申请
    INTERFACE CIRCUIT 审中-公开
    接口电路

    公开(公告)号：US20100257324A1

    公开(公告)日：2010-10-07

    申请号：US12751810

    申请日：2010-03-31

    申请人： Tokuya Osawa ,  Masaru Haraguchi ,  Yoshikazu Morooka ,  Hiroshi Kinoshita

    发明人： Tokuya Osawa ,  Masaru Haraguchi ,  Yoshikazu Morooka ,  Hiroshi Kinoshita

    IPC分类号： G06F12/00

    CPC分类号： G11C8/08 ,  G11C7/1066

    摘要： A variable delay line receives and delays a data strobe signal transferred from a data source side in synchronization with a transfer data by a predetermined period, and produces a delayed data strobe signal and the non-delayed data strobe signal to a detector. The detector determines that a preamble period ends and effective data is transferred, when the delayed data strobe signal is at the L level at the time of rising of the non-delayed data strobe signal from the L level to the H level. According to a result of detection, an interface circuit unit takes in the transfer data and initializes a take-in address. The data strobe signal changes to a high-impedance state when a postamble ends. An influence of a glitch noise is avoided upon this change of the data strobe signal, and the data transfer can be executed fast and accurately.

    摘要翻译： 可变延迟线接收并延迟从数据源侧与传送数据同步预定周期的数据选通信号，并将延迟数据选通信号和非延迟数据选通信号提供给检测器。 当非延迟数据选通信号从L电平上升到H电平时，当延迟的数据选通信号为L电平时，检测器确定前导码周期结束并传送有效数据。 根据检测结果，接口电路单元接收传送数据并初始化接收地址。 当后同步码结束时，数据选通信号变为高阻态。 数据选通信号的变化可以避免毛刺噪声的影响，可以快速准确地执行数据传送。

    Interface circuit
    7.
    发明申请
    Interface circuit 失效
    接口电路

    公开(公告)号：US20080031079A1

    公开(公告)日：2008-02-07

    申请号：US11882117

    申请日：2007-07-30

    申请人： Tokuya Osawa ,  Masaru Haraguchi ,  Yoshikazu Morooka ,  Hiroshi Kinoshita

    发明人： Tokuya Osawa ,  Masaru Haraguchi ,  Yoshikazu Morooka ,  Hiroshi Kinoshita

    IPC分类号： G11C8/18

    CPC分类号： G11C8/08 ,  G11C7/1066

    摘要： A variable delay line receives and delays a data strobe signal transferred from a data source side in synchronization with a transfer data by a predetermined period, and produces a delayed data strobe signal and the non-delayed data strobe signal to a detector. The detector determines that a preamble period ends and effective data is transferred, when the delayed data strobe signal is at the L level at the time of rising of the non-delayed data strobe signal from the L level to the H level. According to a result of detection, an interface circuit unit takes in the transfer data and initializes a take-in address. The data strobe signal changes to a high-impedance state when a postamble ends. An influence of a glitch noise is avoided upon this change of the data strobe signal, and the data transfer can be executed fast and accurately.

    摘要翻译： 可变延迟线接收并延迟从数据源侧与传送数据同步预定周期的数据选通信号，并将延迟数据选通信号和非延迟数据选通信号提供给检测器。 当非延迟数据选通信号从L电平上升到H电平时，当延迟的数据选通信号为L电平时，检测器确定前导码周期结束并传送有效数据。 根据检测结果，接口电路单元接收传送数据并初始化接收地址。 当后同步码结束时，数据选通信号变为高阻态。 数据选通信号的变化可以避免毛刺噪声的影响，可以快速准确地执行数据传送。

    Semiconductor memory device permitting high speed data transfer and high density integration
    8.
    发明授权
    Semiconductor memory device permitting high speed data transfer and high density integration 失效
    半导体存储器件允许高速数据传输和高密度集成

    公开(公告)号：US5586076A

    公开(公告)日：1996-12-17

    申请号：US304899

    申请日：1994-09-13

    申请人： Hiroshi Miyamoto ,  Yoshikazu Morooka ,  Kiyohiro Furutani ,  Shigeru Kikuda

    发明人： Hiroshi Miyamoto ,  Yoshikazu Morooka ,  Kiyohiro Furutani ,  Shigeru Kikuda

    IPC分类号： G11C11/401 ,  G11C7/10 ,  G11C11/409 ,  G11C11/4096 ,  G11C7/00 ,  G11C11/24

    CPC分类号： G11C11/4096 ,  G11C7/10

    摘要： In a memory cell array, data lines are formed into a hierarchical arrangement of sub data lines provided for every block and a main data line common to each block, and a sub data line selected by a column address among sub data lines belonging a block which are simultaneously selected by a row address is connected to a bit line. Accordingly, the sub data line length is reduced, which reduces floating capacitance, reading and writing operations can be conducted at a high speed, and sub data lines can be selectively operated. In addition, power required for charging the sub data lines can be reduced, and entire power consumption by the semiconductor memory device can be reduced as well.

    摘要翻译： 在存储单元阵列中，数据线被形成为每个块提供的子数据线和每个块共同的主数据线的分层布置，以及由属于块的子数据线之间的列地址选择的子数据线 通过行地址同时选择连接到位线。 因此，减少了子数据线的长度，这降低了浮动电容，可以高速地执行读和写操作，并且可以选择性地操作子数据线。 此外，可以减少对子数据线进行充电所需的功率，并且可以减小半导体存储器件的整体功耗。

    Semiconductor memory device connected to memory controller and memory system employing the same
    10.
    发明授权
    Semiconductor memory device connected to memory controller and memory system employing the same 失效
    连接到存储器控制器的半导体存储器件和采用该存储器的存储器系统

    公开(公告)号：US06304502B1

    公开(公告)日：2001-10-16

    申请号：US09215227

    申请日：1998-12-18

    申请人： Naoya Watanabe ,  Yoshikazu Morooka

    发明人： Naoya Watanabe ,  Yoshikazu Morooka

    IPC分类号： G11C700

    CPC分类号： G11C29/76 ,  G11C29/14 ,  G11C29/44

    摘要： Each SLDRAM tests a built in memory section in response to a test execution command supplied from a memory controller and sends a defective address to memory controller. Memory controller stores the defective address of each SLDRAM and accesses only to a normal address and does not access to the defective address. The rate of memory capacity decrease of a main memory can be suppressed compared with a conventional technique where an SLDRAM having a defective address is not accessed.

    摘要翻译： 每个SLDRAM都会根据从存储器控制器提供的测试执行命令来测试内置存储器部分，并将缺陷地址发送到存储器控制器。 存储器控制器存储每个SLDRAM的缺陷地址，并仅访问正常地址，并且不访问有缺陷的地址。 与不存在具有不良地址的SLDRAM的传统技术相比，可以抑制主存储器的存储容量下降的速率。