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    Semiconductor device and its manufacturing method
    1.
    发明授权
    Semiconductor device and its manufacturing method 有权
    半导体器件及其制造方法

    公开(公告)号：US08158483B2

    公开(公告)日：2012-04-17

    申请号：US13075625

    申请日：2011-03-30

    申请人： Taiji Ema ,  Hideyuki Kojima ,  Toru Anezaki

    发明人： Taiji Ema ,  Hideyuki Kojima ,  Toru Anezaki

    IPC分类号： H01L21/336

    CPC分类号： H01L21/823857 ,  H01L21/823892 ,  H01L27/0629

    摘要： A semiconductor device manufacturing method includes, forming isolation region having an aspect ratio of 1 or more in a semiconductor substrate, forming a gate insulating film, forming a silicon gate electrode and a silicon resistive element, forming side wall spacers on the gate electrode, heavily doping a first active region with phosphorus and a second active region and the resistive element with p-type impurities by ion implantation, forming salicide block at 500° C. or lower, depositing a metal layer covering the salicide block, and selectively forming metal silicide layers. The method may further includes, forming a thick and a thin gate insulating films, and performing implantation of ions of a first conductivity type not penetrating the thick gate insulating film and oblique implantation of ions of the opposite conductivity type penetrating also the thick gate insulating film before the formation of side wall spacers.

    摘要翻译： 半导体器件制造方法包括：在半导体衬底中形成具有1以上的纵横比的隔离区域，形成栅极绝缘膜，形成硅栅电极和硅电阻元件，在栅电极上形成侧壁间隔物， 用磷和第二有源区掺杂第一有源区，通过离子注入掺杂p型杂质的电阻元件，在500℃或更低的温度下形成自对准硅化物块，沉积覆盖自对准硅化物块的金属层，并选择性地形成金属硅化物 层。 该方法可以进一步包括：形成厚和薄的栅极绝缘膜，并且执行不穿透厚栅极绝缘膜的第一导电类型的离子的注入和相反导电类型的离子的倾斜注入也穿透厚栅极绝缘膜 在形成侧壁间隔物之前。

    Semiconductor device and its manufacture method
    2.
    发明授权
    Semiconductor device and its manufacture method 有权
    半导体器件及其制造方法

    公开(公告)号：US07605041B2

    公开(公告)日：2009-10-20

    申请号：US12000047

    申请日：2007-12-07

    申请人： Taiji Ema ,  Hideyuki Kojima ,  Toru Anezaki

    发明人： Taiji Ema ,  Hideyuki Kojima ,  Toru Anezaki

    IPC分类号： H01L21/336

    CPC分类号： H01L21/823412 ,  H01L21/823456 ,  H01L21/823493 ,  H01L21/823807 ,  H01L21/823857 ,  H01L21/823878 ,  H01L21/823892

    摘要： Multiple kinds of transistors exhibiting desired characteristics are manufactured in fewer processes. A semiconductor device includes an isolation region reaching a first depth, first and second wells of first conductivity type, a first transistor formed in the first well and having a gate insulating film of a first thickness, and a second transistor formed in the second well and having a gate insulating film of a second thickness less than the first thickness. The first well has a first impurity concentration distribution having an extremum maximum value only at the depth equal to or greater than the first depth. The second well has a second impurity concentration distribution which is superposition of the first impurity concentration distribution, and another impurity concentration distribution which shows an extremum maximum value at a second depth less than the first depth, the superposition shows also an extremum maximum value at the second depth.

    摘要翻译： 具有期望特性的多种晶体管以较少的工艺制造。 半导体器件包括到达第一深度的隔离区域，第一导电类型的第一和第二阱，形成在第一阱中并具有第一厚度的栅极绝缘膜的第一晶体管，以及形成在第二阱中的第二晶体管， 具有第二厚度小于第一厚度的栅极绝缘膜。 第一阱具有仅在等于或大于第一深度的深度处具有极值最大值的第一杂质浓度分布。 第二阱具有第二杂质浓度分布，其是第一杂质浓度分布的叠加，以及在比第一深度小的第二深度处显示极值最大值的另一杂质浓度分布，叠加还显示在 第二深度

    Semiconductor memory device and semiconductor device group
    3.
    发明申请
    Semiconductor memory device and semiconductor device group 有权

    公开(公告)号：US20060017181A1

    公开(公告)日：2006-01-26

    申请号：US10988530

    申请日：2004-11-16

    申请人： Toru Anezaki ,  Tomohiko Tsutsumi ,  Tatsuji Araya ,  Hideyuki Kojima ,  Taiji Ema

    发明人： Toru Anezaki ,  Tomohiko Tsutsumi ,  Tatsuji Araya ,  Hideyuki Kojima ,  Taiji Ema

    IPC分类号： H01L31/109

    CPC分类号： H01L27/1104 ,  G11C5/063 ,  G11C11/412 ,  H01L27/11 ,  Y10S257/903

    摘要： A semiconductor device includes a first CMOS inverter, a second CMOS inverter, a first transfer transistor and a second transfer transistor wherein the first and second transfer transistors are formed respectively in first and second device regions defined on a semiconductor device by a device isolation region so as to extend in parallel with each other, the first transfer transistor contacting with a first bit line at a first bit contact region on the first device region, the second transfer transistor contacting with a second bit line at a second bit contact region on the second device region, wherein the first bit contact region is formed in the first device region such that a center of said the bit contact region is offset toward the second device region, and wherein the second bit contact region is formed in the second device region such that a center of the second bit contact region is offset toward the first device region.

    Semiconductor device and method of manufacturing the same
    4.
    发明授权
    Semiconductor device and method of manufacturing the same 有权
    半导体装置及其制造方法

    公开(公告)号：US08426267B2

    公开(公告)日：2013-04-23

    申请号：US13010416

    申请日：2011-01-20

    申请人： Tomohiko Tsutsumi ,  Taiji Ema ,  Hideyuki Kojima ,  Toru Anezaki

    发明人： Tomohiko Tsutsumi ,  Taiji Ema ,  Hideyuki Kojima ,  Toru Anezaki

    IPC分类号： H01L21/8234 ,  H01L21/8238

    CPC分类号： H01L27/0629 ,  H01L21/823814 ,  H01L21/823857 ,  H01L27/0266 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11546

    摘要： The semiconductor device includes a first MIS transistor including a gate insulating film 92, a gate electrode 108 formed on the gate insulating film 92 and source/drain regions 154, a second MIS transistor including a gate insulating film 96 thicker than the gate insulating film 92, a gate electrode 108 formed on the gate insulating film 96, source/drain regions 154 and a ballast resistor 120 connected to one of the source/drain regions 154, a salicide block insulating film 146 formed on the ballast resistor 120 with an insulating film 92 thinner than the gate insulating film 96 interposed therebetween, and a silicide film 156 formed on the source/drain regions 154.

    摘要翻译： 半导体器件包括第一MIS晶体管，其包括栅极绝缘膜92，形成在栅极绝缘膜92和源极/漏极区154上的栅电极108，包括比栅极绝缘膜92厚的栅极绝缘膜96的第二MIS晶体管 形成在栅极绝缘膜96上的栅极电极108，源极/漏极区域154以及连接到源极/漏极区域154之一的镇流电阻器120，在具有绝缘膜的镇流电阻器120上形成的自对准硅绝缘膜146 92，比其间的栅极绝缘膜96薄，以及形成在源极/漏极区154上的硅化物膜156。

    Semiconductor memory device and semiconductor device group
    7.
    发明授权
    Semiconductor memory device and semiconductor device group 有权
    半导体存储器件和半导体器件组

    公开(公告)号：US07755928B2

    公开(公告)日：2010-07-13

    申请号：US12320861

    申请日：2009-02-06

    申请人： Toru Anezaki ,  Tomohiko Tsutsumi ,  Tatsuji Araya ,  Hideyuki Kojima ,  Taiji Ema

    发明人： Toru Anezaki ,  Tomohiko Tsutsumi ,  Tatsuji Araya ,  Hideyuki Kojima ,  Taiji Ema

    IPC分类号： G11C11/00

    CPC分类号： H01L27/1104 ,  G11C5/063 ,  G11C11/412 ,  H01L27/11 ,  Y10S257/903

    摘要： A semiconductor device includes a first CMOS inverter, a second CMOS inverter, a first transfer transistor and a second transfer transistor wherein the first and second transfer transistors are formed respectively in first and second device regions defined on a semiconductor device by a device isolation region so as to extend in parallel with each other, the first transfer transistor contacting with a first bit line at a first bit contact region on the first device region, the second transfer transistor contacting with a second bit line at a second bit contact region on the second device region, wherein the first bit contact region is formed in the first device region such that a center of said the bit contact region is offset toward the second device region, and wherein the second bit contact region is formed in the second device region such that a center of the second bit contact region is offset toward the first device region.

    摘要翻译： 半导体器件包括第一CMOS反相器，第二CMOS反相器，第一传输晶体管和第二传输晶体管，其中第一和第二传输晶体管分别形成在由器件隔离区限定在半导体器件上的第一和第二器件区域中， 为了彼此并联延伸，第一传输晶体管在第一器件区域上的第一位接触区域处与第一位线接触，第二传输晶体管在第二位线处与第二位线接触，第二位线在第二位接触区域处 器件区域，其中第一位接触区域形成在第一器件区域中，使得所述位接触区域的中心朝向第二器件区域偏移，并且其中第二位接触区域形成在第二器件区域中，使得 第二位接触区域的中心朝向第一器件区域偏移。

    Semiconductor device and its manufacture method
    8.
    发明申请
    Semiconductor device and its manufacture method 有权

    公开(公告)号：US20080090364A1

    公开(公告)日：2008-04-17

    申请号：US12000047

    申请日：2007-12-07

    申请人： Taiji Ema ,  Hideyuki Kojima ,  Toru Anezaki

    发明人： Taiji Ema ,  Hideyuki Kojima ,  Toru Anezaki

    IPC分类号： H01L21/336

    CPC分类号： H01L21/823412 ,  H01L21/823456 ,  H01L21/823493 ,  H01L21/823807 ,  H01L21/823857 ,  H01L21/823878 ,  H01L21/823892

    摘要： Multiple kinds of transistors exhibiting desired characteristics are manufactured in fewer processes. A semiconductor device includes an isolation region reaching a first depth, first and second wells of first conductivity type, a first transistor formed in the first well and having a gate insulating film of a first thickness, and a second transistor formed in the second well and having a gate insulating film of a second thickness less than the first thickness. The first well has a first impurity concentration distribution having an extremum maximum value only at the depth equal to or greater than the first depth. The second well has a second impurity concentration distribution which is superposition of the first impurity concentration distribution, and another impurity concentration distribution which shows an extremum maximum value at a second depth less than the first depth, the superposition shows also an extremum maximum value at the second depth.

    Semiconductor device and its manufacture method
    10.
    发明申请
    Semiconductor device and its manufacture method 有权
    半导体器件及其制造方法

    公开(公告)号：US20050230781A1

    公开(公告)日：2005-10-20

    申请号：US11168553

    申请日：2005-06-29

    申请人： Taiji Ema ,  Hideyuki Kojima ,  Toru Anezaki

    发明人： Taiji Ema ,  Hideyuki Kojima ,  Toru Anezaki

    IPC分类号： H01L21/8234 ,  H01L27/088 ,  H01L29/36 ,  H01L21/336 ,  H01L29/76

    CPC分类号： H01L21/823412 ,  H01L21/823456 ,  H01L21/823493 ,  H01L21/823807 ,  H01L21/823857 ,  H01L21/823878 ,  H01L21/823892

    摘要： Multiple kinds of transistors exhibiting desired characteristics are manufactured in fewer processes. A semiconductor device includes an isolation region reaching a first depth, first and second wells of first conductivity type, a first transistor formed in the first well and having a gate insulating film of a first thickness, and a second transistor formed in the second well and having a gate insulating film of a second thickness less than the first thickness. The first well has a first impurity concentration distribution having an extremum maximum value only at the depth equal to or greater than the first depth. The second well has a second impurity concentration distribution which is superposition of the first impurity concentration distribution, and another impurity concentration distribution which shows an extremum maximum value at a second depth less than the first depth, the superposition shows also an extremum maximum value at the second depth.

    摘要翻译： 具有期望特性的多种晶体管以较少的工艺制造。 半导体器件包括到达第一深度的隔离区域，第一导电类型的第一和第二阱，形成在第一阱中并具有第一厚度的栅极绝缘膜的第一晶体管，以及形成在第二阱中的第二晶体管， 具有第二厚度小于第一厚度的栅极绝缘膜。 第一阱具有仅在等于或大于第一深度的深度处具有极值最大值的第一杂质浓度分布。 第二阱具有第二杂质浓度分布，其是第一杂质浓度分布的叠加，以及在比第一深度小的第二深度处显示极值最大值的另一杂质浓度分布，叠加还显示在 第二深度