公开(公告)号：US12288798B2

公开(公告)日：2025-04-29

申请号：US18360605

申请日：2023-07-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Volume Chien ,  Su-Hua Chang ,  Chia-Yu Wei ,  Zen-Fong Huang ,  Chi-Cherng Jeng

IPC: H01L27/146 ,  H01L31/0216

Abstract: An image sensor includes a pixel array, a dielectric layer, a plurality of first conductive shielding regions, and a plurality of second conductive shielding regions. The pixel array includes photodiodes within a substrate. The dielectric layer is over the substrate. From a plan view, the first conductive shielding regions are adjacent four corners of the pixel array, and the second conductive shielding regions are adjacent four sides of the pixel array. The second conductive region has a length-to-width ratio greater than a length-to-width ratio of the first conductive region.

公开(公告)号：US11810939B2

公开(公告)日：2023-11-07

申请号：US17744175

申请日：2022-05-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Volume Chien ,  Su-Hua Chang ,  Chia-Yu Wei ,  Zen-Fong Huang ,  Chi-Cherng Jeng

IPC: H01L27/146 ,  H01L31/0216

CPC classification number: H01L27/1464 ,  H01L27/14623 ,  H01L27/14627 ,  H01L27/14632 ,  H01L27/14687 ,  H01L31/02164

Abstract: A backside illuminated image sensor device with a shielding layer and a manufacturing method thereof are provided. In the backside illuminated image senor device, a patterned conductive shielding layer is formed on a dielectric layer on a backside surface of a semiconductor substrate and surrounding a pixel array on a front side surface of the semiconductor substrate.

公开(公告)号：US10957695B2

公开(公告)日：2021-03-23

申请号：US16657528

申请日：2019-10-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Barn Chen ,  Chi-Cherng Jeng ,  Shiu-Ko Jangjian ,  Ting-Huang Kuo

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/06

Abstract: The present disclosure describes an exemplary asymmetric CPP layout for a semiconductor structure with a different gate pitch over the source and the drain regions to mitigate gate-to-gate parasitic capacitances over the drain region, thus improving cutoff frequency. For example, the semiconductor structure can include a fin on a substrate. The semiconductor structure can also include first and second gate structures formed on the fin and separated by a first space. The semiconductor structure can also include a third gate structure formed on the fin between the first and the second gate structures. The third gate structure can be separated from the first gate structure by a second pitch and separated from the second gate structure by a third pitch that is greater than the second pitch. The semiconductor structure further includes a source region formed between the first and third gate structures, and a drain region formed between the third and the second gate structures.

公开(公告)号：US10276620B2

公开(公告)日：2019-04-30

申请号：US14192258

申请日：2014-02-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Volume Chien ,  Yun-Wei Cheng ,  Zhe-Ju Liu ,  Kuo-Cheng Lee ,  Chi-Cherng Jeng ,  Chuan-Pu Liu

IPC: H01L27/146

Abstract: Embodiments of the disclosure provide an image sensor device. The image sensor device includes a semiconductor substrate including a front surface, a back surface opposite to the front surface, a light-sensing region close to the front surface, and a trench adjacent to the light-sensing region. The image sensor device includes a light-blocking structure positioned in the trench to absorb or reflect incident light.

公开(公告)号：US10269845B2

公开(公告)日：2019-04-23

申请号：US15380764

申请日：2016-12-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Volume Chien ,  Yun-Wei Cheng ,  Shiu-Ko Jangjian ,  Zhe-Ju Liu ,  Kuo-Cheng Lee ,  Chi-Cherng Jeng

IPC: H01L27/146 ,  H01L31/0232 ,  H01L31/0216

Abstract: A method for forming an image sensor device is provided. The method includes forming a photodetector in a semiconductor substrate and forming a shielding layer over the semiconductor substrate. The method also includes forming a dielectric layer over the shielding layer and partially removing the dielectric layer to form a recess. The method further includes partially removing the shielding layer through the recess. In addition, the method includes forming a filter in the recess after the shielding layer is partially removed.

公开(公告)号：US10109739B2

公开(公告)日：2018-10-23

申请号：US15099606

申请日：2016-04-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Hua Kuan ,  Chen-Chieh Chiang ,  Chi-Cherng Jeng

IPC: H01L29/78 ,  H01L29/06

Abstract: A FinFET including a substrate, a plurality of insulators and a gate stack is provided. The substrate comprises a plurality of trenches and at least one semiconductor fin between the trenches, wherein the semiconductor fin comprises at least one groove, and the at least one groove is located on a top surface of the semiconductor fin. The insulators are disposed in the trenches. The gate stack partially covers the semiconductor fin, the at least one groove and the insulators.

公开(公告)号：US10056426B2

公开(公告)日：2018-08-21

申请号：US13936240

申请日：2013-07-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yun-Wei Cheng ,  Volume Chien ,  I-I Cheng ,  Chi-Cherng Jeng

IPC: H01L27/146 ,  G02B3/00

CPC classification number: H01L27/14685 ,  G02B3/0056 ,  H01L27/1462 ,  H01L27/14621 ,  H01L27/14627

Abstract: A light guide grid can include a grid structure having a plurality of intersecting grid lines, each grid line having a width w, and a plurality of openings for photosensor elements between intersecting grid lines. The grid structure has a diagonal grid width between two adjacent ones of the plurality of openings in a diagonal direction. The diagonal grid width has a value exceeding approximately √3 w. An image sensor can include a light guide grid having a grid structure as described above and further include a micro-lens such as a sinking micro-lens and a color filter. A method of fabricating a light guide grid can include forming a grid above at least one photo sensor, the grid having intersecting grid lines of width w and a diagonal grid width in a diagonal direction having a value exceeding approximately √3 w.

公开(公告)号：US09824929B2

公开(公告)日：2017-11-21

申请号：US15382478

申请日：2016-12-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shiu-Ko Jangjian ,  Ren-Hau Yu ,  Chi-Cherng Jeng

IPC: H01L21/8234 ,  H01L27/092 ,  H01L29/49 ,  H01L21/285

CPC classification number: H01L21/82345 ,  H01L21/28088 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L27/0924 ,  H01L29/4966 ,  H01L29/785

Abstract: A semiconductor device includes a n-type gate structure over a first semiconductor fin, in which the n-type gate structure is fluorine incorporated and includes a n-type work function metal layer overlying the first high-k dielectric layer. The n-type work function metal layer includes a TiAl (titanium aluminum) alloy, in which an atom ratio of Ti (titanium) to Al (aluminum) is in a range substantially from 1 to 3. The semiconductor device further includes a p-type gate structure over a second semiconductor fin, in which the p-type gate structure is fluorine incorporated includes a p-type work function metal layer overlying the second high-k dielectric layer. The p-type work function metal layer includes titanium nitride (TiN), in which an atom ratio of Ti to N (nitrogen) is in a range substantially from 1:0.9 to 1:1.1.

公开(公告)号：US20170301795A1

公开(公告)日：2017-10-19

申请号：US15099606

申请日：2016-04-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Hua Kuan ,  Chen-Chieh Chiang ,  Chi-Cherng Jeng

IPC: H01L29/78 ,  H01L29/06

CPC classification number: H01L29/7851 ,  H01L29/0649 ,  H01L29/0688 ,  H01L29/7853

Abstract: A FinFET including a substrate, a plurality of insulators and a gate stack is provided. The substrate comprises a plurality of trenches and at least one semiconductor fin between the trenches, wherein the semiconductor fin comprises at least one groove, and the at least one groove is located on a top surface of the semiconductor fin. The insulators are disposed in the trenches. The gate stack partially covers the semiconductor fin, the at least one groove and the insulators.

公开(公告)号：US09768073B1

公开(公告)日：2017-09-19

申请号：US15054134

申请日：2016-02-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Chung Lin ,  Chen-Chieh Chiang ,  Chi-Cherng Jeng

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/423 ,  H01L27/092

CPC classification number: H01L21/823807 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/1033 ,  H01L29/4236

Abstract: Provided is a semiconductor device having dual channels including a first portion and a second portion sharing a buried gate pillar. The buried gate pillar extends from a first surface of a substrate toward a second surface opposite to the first surface. The first portion includes the buried gate pillar, a first gate dielectric layer at a first sidewall of the buried gate pillar and a first doped region set aside the first gate dielectric layer. A first channel is provided in the substrate between the first gate dielectric layer and the first doped region set. The second portion includes the buried gate pillar, a second gate dielectric layer at a second sidewall of the buried gate pillar and a second doped region set aside the second gate dielectric layer. A second channel is provided in the substrate between the second gate dielectric layer and the second doped region set.