公开(公告)号：US09337126B2

公开(公告)日：2016-05-10

申请号：US14091610

申请日：2013-11-27

Applicant: Taiwan Semiconductor Manufacturing CO., LTD.

Inventor： Chen-Hao Li ,  Ying-Han Chiou ,  Chi-Yen Lin

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/00

CPC classification number: H01L23/481 ,  H01L21/76838 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/81193 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/37001 ,  H01L2924/00014

Abstract: An integrated circuit and a method of fabricating the integrated circuit are provided. In various embodiments, the integrated circuit includes a first substrate, a second substrate, and a bump pad. The first substrate has at least one active device and a plurality of first metallic pads electrically connected to the active device. The first substrate has front-end-of-line processing layers without back-end-of-line processing layers over the front-end-of-line processing layers. The second substrate has a semiconductor substrate and an interconnect structure disposed on the semiconductor substrate, and the interconnect structure has at least one second metallic pad. The second substrate does not include any active devices. The bump pad is sandwiched by the first substrate and the second substrate. The active device and the first metallic pad of the first substrate are electrically connected to the second metallic pad of the second substrate through the bump pad.

Abstract translation: 提供集成电路和制造集成电路的方法。 在各种实施例中，集成电路包括第一衬底，第二衬底和凸块焊盘。 第一基板具有至少一个有源器件和电连接到有源器件的多个第一金属焊盘。 第一衬底具有在行前处理层之上没有后端行处理层的前端处理层。 第二衬底具有设置在半导体衬底上的半导体衬底和互连结构，并且互连结构具有至少一个第二金属衬垫。 第二基板不包括任何有源器件。 凸块由第一基板和第二基板夹持。 第一基板的有源器件和第一金属焊盘通过凸块焊接电连接到第二衬底的第二金属焊盘。

公开(公告)号：US20150145119A1

公开(公告)日：2015-05-28

申请号：US14091610

申请日：2013-11-27

Applicant: Taiwan Semiconductor Manufacturing CO., LTD.

Inventor： Chen-Hao Li ,  Ying-Han Chiou ,  Chi-Yen Lin

IPC: H01L23/48 ,  H01L23/00 ,  H01L21/768

CPC classification number: H01L23/481 ,  H01L21/76838 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/81193 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/37001 ,  H01L2924/00014

Abstract: An integrated circuit and a method of fabricating the integrated circuit are provided. In various embodiments, the integrated circuit includes a first substrate, a second substrate, and a bump pad. The first substrate has at least one active device and a plurality of first metallic pads electrically connected to the active device. The first substrate has front-end-of-line processing layers without back-end-of-line processing layers over the front-end-of-line processing layers. The second substrate has a semiconductor substrate and an interconnect structure disposed on the semiconductor substrate, and the interconnect structure has at least one second metallic pad. The second substrate does not include any active devices. The bump pad is sandwiched by the first substrate and the second substrate. The active device and the first metallic pad of the first substrate are electrically connected to the second metallic pad of the second substrate through the bump pad.

Abstract translation: 提供集成电路和制造集成电路的方法。 在各种实施例中，集成电路包括第一衬底，第二衬底和凸块焊盘。 第一基板具有至少一个有源器件和电连接到有源器件的多个第一金属焊盘。 第一衬底具有在行前处理层之上没有后端行处理层的前端处理层。 第二衬底具有设置在半导体衬底上的半导体衬底和互连结构，并且互连结构具有至少一个第二金属衬垫。 第二基板不包括任何有源器件。 凸块由第一基板和第二基板夹持。 第一基板的有源器件和第一金属焊盘通过凸块焊接电连接到第二衬底的第二金属焊盘。

公开(公告)号：US20240387304A1

公开(公告)日：2024-11-21

申请号：US18318985

申请日：2023-05-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Huan Hsin ,  Ying-Han Chiou

IPC: H01L23/10 ,  H01L21/56 ,  H01L21/8234 ,  H01L23/00 ,  H01L23/29 ,  H01L23/31 ,  H01L23/528 ,  H01L25/10

Abstract: A semiconductor structure with a protective ring and the method of forming the same are provided. The semiconductor structure may comprise an integrated circuit die and an encapsulant encircling the integrated circuit die in a top down view. The integrated circuit die may comprise a substrate having an electrical device, an interconnect structure on the substrate and electrically coupled to the electrical device, a seal ring in the interconnect structure and encircling the electrical device in the top down view, and a protective ring at least partially embedded in the substrate. The protective ring may encircle the seal ring in a top down view and may comprise a material different from a material of the substrate.