公开(公告)号：US10971577B2

公开(公告)日：2021-04-06

申请号：US16438266

申请日：2019-06-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao Chieh Li ,  Hao-chieh Chan

IPC: H01L49/02 ,  H03B5/12 ,  H01L27/06 ,  H01L27/092

Abstract: According to some embodiments, an integrated circuit device is disclosed. The integrated circuit device include at least one inductor having at least one turn, a magnetic coupling ring positioned adjacent to the at least one inductor, the magnetic coupling ring comprising at least two magnetic coupling turns, the at least two magnetic coupling turns are disposed adjacent to the at least one turn to enable magnetic coupling between the at least two magnetic coupling turns and the at least one turn. The integrated circuit device also includes a power electrode and a ground electrode, wherein the power electrode and the ground electrode are coupled to the at least one inductor and the magnetic coupling ring to provide a first current in the at least one inductor having a direction opposite to a second current in the magnetic coupling ring to cancel at least a portion of a magnetic field generated by the at least one inductor.

公开(公告)号：US10439018B2

公开(公告)日：2019-10-08

申请号：US15151098

申请日：2016-05-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD

Inventor： Chao Chieh Li ,  Hao-chieh Chan

IPC: H03B5/12 ,  H01L27/06 ,  H01L49/02 ,  H01L27/092

Abstract: According to some embodiments, an integrated circuit device is disclosed. The integrated circuit device include at least one inductor having at least one turn, a magnetic coupling ring positioned adjacent to the at least one inductor, the magnetic coupling ring comprising at least two magnetic coupling turns, the at least two magnetic coupling turns are disposed adjacent to the at least one turn to enable magnetic coupling between the at least two magnetic coupling turns and the at least one turn The integrated circuit device also includes a power electrode and a ground electrode, wherein the power electrode and the ground electrode are coupled to the at least one inductor and the magnetic coupling ring to provide a first current in the at least one inductor having a direction opposite to a second current in the magnetic coupling ring to cancel at least a portion of a magnetic field generated by the at least one inductor.

公开(公告)号：US11749710B2

公开(公告)日：2023-09-05

申请号：US17222816

申请日：2021-04-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao Chieh Li ,  Hao-chieh Chan

IPC: H03B5/12 ,  H01L27/06 ,  H01L27/092 ,  H01L49/02

CPC classification number: H01L28/10 ,  H01L27/0617 ,  H01L27/0623 ,  H01L27/0641 ,  H01L27/092 ,  H01L28/40 ,  H03B5/124 ,  H03B5/1212 ,  H03B5/1228 ,  H03B5/1296

Abstract: According to some embodiments, an integrated circuit device is disclosed. The integrated circuit device include at least one inductor having at least one turn, a magnetic coupling ring positioned adjacent to the at least one inductor, the magnetic coupling ring comprising at least two magnetic coupling turns, the at least two magnetic coupling turns are disposed adjacent to the at least one turn to enable magnetic coupling between the at least two magnetic coupling turns and the at least one turn The integrated circuit device also includes a power electrode and a ground electrode, wherein the power electrode and the ground electrode are coupled to the at least one inductor and the magnetic coupling ring to provide a first current in the at least one inductor having a direction opposite to a second current in the magnetic coupling ring to cancel at least a portion of a magnetic field generated by the at least one inductor.

公开(公告)号：US09035464B2

公开(公告)日：2015-05-19

申请号：US14014472

申请日：2013-08-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao Chieh Li ,  Ruey-Bin Sheen ,  Chih-Hsien Chang

IPC: H01L29/04 ,  H01L23/48 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L23/481 ,  H01L21/76805 ,  H01L23/5226 ,  H01L25/0657 ,  H01L2225/06527 ,  H01L2225/06544 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A die stack comprises a first integrated circuit (IC) die having at least a first device comprising a first source, a first drain and a first gate electrode above a first channel region between the first source and the first drain. A second IC die has at least a second device comprising a second source, a second drain and a second gate electrode above a second channel region between the second source and the second drain. The second gate electrode is connected to the first gate electrode by a path including a first through substrate via (TSV), the second drain connected to the first source by a path including a second TSV.

Abstract translation: 芯片堆叠包括具有至少第一器件的第一集成电路（IC）管芯，该第一器件包括在第一源极和第一漏极之间的第一沟道区域之上的第一源极，第一漏极和第一栅极电极。 第二IC管芯具有至少第二器件，其包括在第二源极和第二漏极之间的第二沟道区域上方的第二源极，第二漏极和第二栅极电极。 第二栅电极通过包括第一贯穿衬底通孔（TSV）的路径连接到第一栅电极，第二漏极通过包括第二TSV的路径连接到第一源极。

公开(公告)号：US20210225999A1

公开(公告)日：2021-07-22

申请号：US17222816

申请日：2021-04-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao Chieh Li ,  Hao-chieh Chan

IPC: H01L49/02 ,  H03B5/12 ,  H01L27/06 ,  H01L27/092

Abstract: According to some embodiments, an integrated circuit device is disclosed. The integrated circuit device include at least one inductor having at least one turn, a magnetic coupling ring positioned adjacent to the at least one inductor, the magnetic coupling ring comprising at least two magnetic coupling turns, the at least two magnetic coupling turns are disposed adjacent to the at least one turn to enable magnetic coupling between the at least two magnetic coupling turns and the at least one turn The integrated circuit device also includes a power electrode and a ground electrode, wherein the power electrode and the ground electrode are coupled to the at least one inductor and the magnetic coupling ring to provide a first current in the at least one inductor having a direction opposite to a second current in the magnetic coupling ring to cancel at least a portion of a magnetic field generated by the at least one inductor.

公开(公告)号：US10121781B2

公开(公告)日：2018-11-06

申请号：US15431934

申请日：2017-02-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chao Chieh Li ,  Ruey-Bin Sheen ,  Chih-Hsien Chang

IPC: H01L27/06 ,  H01L25/065 ,  H01L25/00 ,  H01L23/48 ,  H01L21/768 ,  H01L23/528 ,  H01L21/8234 ,  H01L23/522 ,  H01L27/088 ,  H01L27/112

Abstract: A die stack comprises a first integrated circuit (IC) die having at least a first device comprising a first source, a first drain and a first gate electrode above a first channel region between the first source and the first drain. A second IC die has at least a second device comprising a second source, a second drain and a second gate electrode above a second channel region between the second source and the second drain. The second gate electrode is connected to the first gate electrode by a path including a first through substrate via (TSV), the second drain connected to the first source by a path including a second TSV.

公开(公告)号：US09595474B2

公开(公告)日：2017-03-14

申请号：US14707420

申请日：2015-05-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chao Chieh Li ,  Ruey-Bin Sheen ,  Chih-Hsien Chang

IPC: H01L21/822 ,  H01L25/00 ,  H01L25/065 ,  H01L23/48 ,  H01L27/06 ,  H01L27/088

CPC classification number: H01L27/0688 ,  H01L21/76897 ,  H01L21/76898 ,  H01L21/8221 ,  H01L21/823475 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/528 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/088 ,  H01L27/1128 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A die stack comprises a first integrated circuit (IC) die having at least a first device comprising a first source, a first drain and a first gate electrode above a first channel region between the first source and the first drain. A second IC die has at least a second device comprising a second source, a second drain and a second gate electrode above a second channel region between the second source and the second drain. The second gate electrode is connected to the first gate electrode by a path including a first through substrate via (TSV), the second drain connected to the first source by a path including a second TSV.

Abstract translation: 芯片堆叠包括具有至少第一器件的第一集成电路（IC）管芯，该第一器件包括在第一源极和第一漏极之间的第一沟道区域之上的第一源极，第一漏极和第一栅极电极。 第二IC管芯具有至少第二器件，其包括在第二源极和第二漏极之间的第二沟道区域上方的第二源极，第二漏极和第二栅电极。 第二栅电极通过包括第一贯穿衬底通孔（TSV）的路径连接到第一栅电极，第二漏极通过包括第二TSV的路径连接到第一源极。