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公开(公告)号：US20200044873A1
公开(公告)日：2020-02-06
申请号：US16594745
申请日：2019-10-07
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chien-Chen LIN , Shih-Lien Linus Lu , Wei-Min Chan
Abstract: A memory device includes a memory block that includes a plurality of memory bits, wherein each bit is configured to present a first logical state; and an authentication circuit, coupled to the plurality of memory bits, wherein the authentication circuit is configured to access a first bit under either a reduced read margin or a reduced write margin condition to determine a stability of the first bit by detecting whether the first logical state flips to a second logical state, and based on the determined stability of at least the first bit, to generate a physically unclonable function (PUF) signature.
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公开(公告)号：US20180102163A1
公开(公告)日：2018-04-12
申请号：US15288342
申请日：2016-10-07
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chien-Chen LIN , Wei-Min Chan , Chih-Yu Lin , Shih-Lien Linus Lu , Yen-Huei Chen
IPC: G11C11/419 , G11C11/418 , H04L9/32
CPC classification number: G11C11/419 , G09C1/00 , G11C7/20 , G11C7/24 , G11C11/413 , G11C11/418 , G11C2029/4402 , H04L9/3278
Abstract: A memory device includes a memory cell array comprising a plurality of memory cells wherein each of the plurality of memory cells is configured to be in a data state, and a physically unclonable function (PUF) generator. The PUF generator further includes a first sense amplifier, coupled to the plurality of memory cells, wherein while the plurality of memory cells are being accessed, the first sense amplifier is configured to compare accessing speeds of first and second memory cells of the plurality of memory cells, and based on the comparison, provide a first output signal for generating a first PUF signature.
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公开(公告)号：US20220236894A1
公开(公告)日：2022-07-28
申请号：US17717491
申请日：2022-04-11
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yu-Hao HSU , Cheng Hung LEE , Chen-Lin YANG , Chiting CHENG , Fu-An WU , Hung-Jen LIAO , Jung-Ping YANG , Jonathan Tsung-Yung CHANG , Wei Min CHAN , Yen-Huei CHEN , Yangsyu LIN , Chien-Chen LIN
Abstract: Various embodiments for configurable memory storage systems are disclosed. The configurable memory storages selectively choose an operational voltage signal from among multiple voltage signals to dynamically control various operational parameters. For example, the configurable memory storages selectively choose a maximum voltage signal from among the multiple voltage signals to maximize read/write speed. As another example, the configurable memory storages selectively choose a minimum voltage signal from among the multiple voltage signals to minimize power consumption.
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Patent Agency Ranking
公开(公告)号：US20180151226A1
公开(公告)日：2018-05-31
申请号：US15799253
申请日：2017-10-31
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Hidehiro FUJIWARA , Hung-Jen LIAO , Hsien-Yu PAN , Chih-Yu LIN , Yen-Huei CHEN , Chien-Chen LIN
Abstract: A cell structure is disclosed. The cell structure includes a first unit comprising a first group of transistors and a first data latch, a second unit comprising a second group of transistors and a second data latch a read port unit comprising a plurality of p-type transistors, a search line and a complementary search line, the search line and the complementary search line function as input of the cell structure, and a master line, the master line functions as an output of the cell structure, the first unit is coupled to the second unit, both the first and the second units are coupled to the read port unit. According to some embodiments, the first data latch comprises a first and a second p-type transistors, a first and a second n-type transistors.
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公开(公告)号：US20180102907A1
公开(公告)日：2018-04-12
申请号：US15288382
申请日：2016-10-07
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chien-Chen LIN , Shih-Lien Linus LU , Wei-Min CHAN
CPC classification number: H04L9/3278 , G06F12/1408 , G06F21/44 , G06F21/73 , G06F2212/1052 , G06F2212/402
Abstract: A memory device includes a memory block that includes a plurality of memory bits, wherein each bit is configured to present a first logical state; and an authentication circuit, coupled to the plurality of memory bits, wherein the authentication circuit is configured to access a first bit under either a reduced read margin or a reduced write margin condition to determine a stability of the first bit by detecting whether the first logical state flips to a second logical state, and based on the determined stability of at least the first bit, to generate a physically unclonable function (PUF) signature.
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公开(公告)号：US20200081636A1
公开(公告)日：2020-03-12
申请号：US16685722
申请日：2019-11-15
Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.
Inventor： Yu-Hao HSU , Cheng Hung LEE , Chen-Lin YANG , Chiting CHENG , Fu-An WU , Hung-Jen LIAO , Jung-Ping YANG , Jonathan Tsung-Yung CHANG , Wei Min CHAN , Yen-Huei CHEN , Yangsyu LIN , Chien-Chen LIN
Abstract: Various embodiments for configurable memory storage systems are disclosed. The configurable memory storages selectively choose an operational voltage signal from among multiple operational voltage signals to dynamically control various operational parameters. For example, the configurable memory storages selectively choose a maximum operational voltage signal from among the multiple operational voltage signals to maximize read/write speed. As another example, the configurable memory storages selectively choose a minimum operational voltage signal from among the multiple operational voltage signals to minimize power consumption.
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公开(公告)号：US20190096478A1
公开(公告)日：2019-03-28
申请号：US16202584
申请日：2018-11-28
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chien-Chen LIN , Wei-Min Chan , Chih-Yu Lin , Shih-Lien Linus Lu , Yen-Huei Chen
IPC: G11C11/419 , H04L9/32 , G11C11/418 , G09C1/00 , G11C11/413 , G11C7/24 , G11C7/20 , G11C29/44
CPC classification number: G11C11/419 , G09C1/00 , G11C7/20 , G11C7/24 , G11C11/413 , G11C11/418 , G11C2029/4402 , H04L9/3278
Abstract: A memory device includes a memory cell array comprising a plurality of memory cells wherein each of the plurality of memory cells is configured to be in a data state, and a physically unclonable function (PUF) generator. The PUF generator further includes a first sense amplifier, coupled to the plurality of memory cells, wherein while the plurality of memory cells are being accessed, the first sense amplifier is configured to compare accessing speeds of first and second memory cells of the plurality of memory cells, and based on the comparison, provide a first output signal for generating a first PUF signature.
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公开(公告)号：US20210200452A1
公开(公告)日：2021-07-01
申请号：US17201931
申请日：2021-03-15
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yu-Hao HSU , Cheng Hung LEE , Chen-Lin YANG , Chiting CHENG , Fu-An WU , Hung-Jen LIAO , Jung-Ping YANG , Jonathan Tsung-Yung CHANG , Wei Min CHAN , Yen-Huei CHEN , Yangsyu LIN , Chien-Chen LIN
Abstract: Various embodiments for configurable memory storage systems are disclosed. The configurable memory storages selectively choose an operational voltage signal from among multiple operational voltage signals to dynamically control various operational parameters. For example, the configurable memory storages selectively choose a maximum operational voltage signal from among the multiple operational voltage signals to maximize read/write speed. As another example, the configurable memory storages selectively choose a minimum operational voltage signal from among the multiple operational voltage signals to minimize power consumption.
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