公开(公告)号：US20240213340A1

公开(公告)日：2024-06-27

申请号：US18599779

申请日：2024-03-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shahaji B. MORE ,  Cheng-Han LEE

IPC: H01L29/417 ,  H01L21/8234 ,  H01L29/04 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/41791 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L29/04 ,  H01L29/66795 ,  H01L29/785

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a gate structure over the substrate, and a source/drain (S/D) region adjacent to the gate structure. The S/D region can include first and second side surfaces separated from each other. The S/D region can further include top and bottom surfaces between the first and second side surfaces. A first separation between the top and bottom surfaces can be greater than a second separation between the first and second side surfaces.

公开(公告)号：US20220037520A1

公开(公告)日：2022-02-03

申请号：US16984075

申请日：2020-08-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shahaji B. More ,  Shih-Chieh CHANG ,  Cheng-Han LEE ,  Pei-Shan LEE

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/417

Abstract: A semiconductor device includes semiconductor wires or sheets disposed over a substrate, a source/drain epitaxial layer in contact with the semiconductor wires or sheets, a gate dielectric layer disposed on and wrapping around each channel region of the semiconductor wires or sheets, a gate electrode layer disposed on the gate dielectric layer and wrapping around each channel region, and insulating spacers disposed in spaces, respectively. The spaces are defined by adjacent semiconductor wires or sheets, the gate electrode layer and the source/drain region. The source/drain epitaxial layer includes multiple doped SiGe layers having different Ge contents and at least one of the source/drain epitaxial layers is non-doped SiGe or Si.

公开(公告)号：US20180108775A1

公开(公告)日：2018-04-19

申请号：US15292428

申请日：2016-10-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shahaji B. MORE ,  Zheng-Yang PAN ,  Chun-Chieh WANG ,  Cheng-Han LEE ,  Shih-Chieh CHANG

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/267 ,  H01L29/36 ,  H01L29/417 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L21/823418 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/267 ,  H01L29/36 ,  H01L29/41783 ,  H01L29/66636

Abstract: Structures of a semiconductor device are provided. The semiconductor device includes a substrate, a gate structure over the substrate, and a first recess and a second recess in the substrate and at opposite sides of the gate structure. The semiconductor device also includes two source/drain structures over the first recess and the second recess respectively. At least one of the source/drain structures includes a first doped region partially filling in the first recess, a second doped region over the first doped region, and a third doped region over the second doped region. The second doped region contains more dopants than the first doped region or the third doped region.

公开(公告)号：US20220149157A1

公开(公告)日：2022-05-12

申请号：US17582727

申请日：2022-01-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shahaji B. MORE ,  Huai-Tei YANG ,  Zheng-Yang PAN ,  Shih-Chieh CHANG ,  Chun-Chieh WANG ,  Cheng-Han LEE

IPC: H01L29/10 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/74 ,  H01L21/308 ,  H01L27/092 ,  H01L29/66 ,  H01L21/3065 ,  H01L29/78 ,  H01L29/06

Abstract: The present disclosure describes an exemplary fin structure formed on a substrate. The disclosed fin structure comprises an n-type doped region formed on a top portion of the substrate, a silicon epitaxial layer on the n-type doped region, and an epitaxial stack on the silicon epitaxial layer, wherein the epitaxial stack comprises a silicon-based seed layer in physical contact with the silicon epitaxial layer. The fin structure can further comprise a liner surrounding the n-type doped region, and a dielectric surrounding the liner.

公开(公告)号：US20190148552A1

公开(公告)日：2019-05-16

申请号：US16231719

申请日：2018-12-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shahaji B. MORE ,  Zheng-Yang PAN ,  Chun-Chieh WANG ,  Cheng-Han LEE ,  Shih-Chieh CHANG

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/165 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/36 ,  H01L29/267 ,  H01L29/08 ,  H01L21/8238

Abstract: A method for forming a semiconductor device is provided. The method includes forming a gate stack to partially cover a semiconductor structure. The method also includes forming a first semiconductor material over the semiconductor structure. The method further includes forming a second semiconductor material over the first semiconductor material. In addition, the method includes forming a third semiconductor material over the second semiconductor material. The first semiconductor material and the third semiconductor material together surround the second semiconductor material. The second semiconductor material has a greater dopant concentration than that of the first semiconductor material or that of the third semiconductor material.

公开(公告)号：US20190148527A1

公开(公告)日：2019-05-16

申请号：US15962348

申请日：2018-04-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shahaji B. MORE ,  Shih-Chieh CHANG ,  Cheng-Han LEE ,  Huai-Tei YANG

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/167 ,  H01L29/24 ,  H01L21/3065 ,  H01L21/265 ,  H01L29/78

Abstract: Semiconductor structures and method for forming the same are provide. The method includes forming a gate structure over a substrate and forming a recess in the substrate adjacent to the gate structure. The method further includes forming a doped region at a sidewall and a bottom surface of the recess and partially removing the doped region to modify a shape of the recess. The method further includes forming a source/drain structure over a remaining portion of the doped region.

公开(公告)号：US20180294357A1

公开(公告)日：2018-10-11

申请号：US16004727

申请日：2018-06-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shahaji B. MORE ,  Zheng-Yang PAN ,  Chun-Chieh WANG ,  Cheng-Han LEE ,  Shih-Chieh CHANG

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/417 ,  H01L21/8234 ,  H01L29/267 ,  H01L29/08 ,  H01L29/36

CPC classification number: H01L29/7848 ,  H01L21/823418 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/267 ,  H01L29/36 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/7834

Abstract: Structures and formation methods of a semiconductor device are provided. The semiconductor device structure includes a substrate and a gate structure over the substrate. The semiconductor device structure also includes a source/drain structure near the gate structure. The source/drain structure has an inner portion and an outer portion surrounding an entirety of the inner portion. The inner portion has a greater average dopant concentration than that of the outer portion.

公开(公告)号：US20180151357A1

公开(公告)日：2018-05-31

申请号：US15399143

申请日：2017-01-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shahaji B. MORE ,  Zheng-Yang PAN ,  Cheng-Han LEE ,  Shih-Chieh CHANG ,  Chandrashekhar Prakash SAVANT

IPC: H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/41 ,  H01L29/786 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L21/02603 ,  H01L21/02524 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/02653 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/1037 ,  H01L29/1054 ,  H01L29/413 ,  H01L29/66227 ,  H01L29/66742 ,  H01L29/78696

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a substrate, a first source portion and a first drain portion over the substrate, and a first semiconductor nanowire over the substrate and between the first source portion and the first drain portion. The first semiconductor nanowire includes a first portion over the substrate and a second portion over the first portion, and the first portion has a first width, and the second portion has a second width, and the second width is less than the first width. The semiconductor device structure also includes a first gate structure over the second portion of the first semiconductor nanowire.

公开(公告)号：US20210391450A1

公开(公告)日：2021-12-16

申请号：US16902170

申请日：2020-06-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shahaji B. MORE ,  Chien LIN ,  Cheng-Han LEE ,  Shih-Chieh CHANG ,  Shu KUAN

IPC: H01L29/66 ,  H01L21/306 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/10 ,  H01L29/78 ,  H01L29/161

Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space to cover the inner spacer. At least one of the first semiconductor layers has a composition which changes along a stacked direction of the first semiconductor layers and second semiconductor layers.

公开(公告)号：US20210273047A1

公开(公告)日：2021-09-02

申请号：US16934887

申请日：2020-07-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shu KUAN ,  Shahaji B. MORE ,  Chien LIN ,  Cheng-Han LEE ,  Shih-Chieh CHANG

IPC: H01L29/06 ,  H01L29/423

Abstract: In a method of manufacturing a semiconductor device, a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked is formed, a sacrificial gate structure is formed over the fin structure, a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space, the first semiconductor layers are laterally etched through the source/drain space, and a source/drain epitaxial layer is formed in the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers and at least one of the spacer has width changes along vertical direction of device. At least one of the first semiconductor layers has a composition different from another of the first semiconductor layers.