公开(公告)号：US12068227B2

公开(公告)日：2024-08-20

申请号：US18196988

申请日：2023-05-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Jung Chen ,  Cheng-Hung Wang ,  Tsung-Lin Lee ,  Shiuan-Jeng Lin ,  Chun-Ming Lin ,  Wen-Chih Chiang

IPC: H01L23/48 ,  H01L21/02 ,  H01L21/311 ,  H01L21/762 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L23/58 ,  H01L29/06

CPC classification number: H01L23/481 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/31116 ,  H01L21/76283 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/528 ,  H01L23/53257 ,  H01L23/53271 ,  H01L23/585 ,  H01L29/0649

Abstract: Structures and methods for reducing process charging damages are disclosed. In one example, a silicon-on-insulator (SOI) structure is disclosed. The SOI structure includes: a substrate, a polysilicon region and an etch stop layer. The substrate includes: a handle layer, an insulation layer arranged over the handle layer, and a buried layer arranged over the insulation layer. The polysilicon region extends downward from an upper surface of the buried layer and terminates in the handle layer. The etch stop layer is located on the substrate. The etch stop layer is in contact with both the substrate and the polysilicon region.

公开(公告)号：US12074169B2

公开(公告)日：2024-08-27

申请号：US17876409

申请日：2022-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Jung Chen ,  Tsung-Lin Lee ,  Chung-Ming Lin ,  Wen-Chih Chiang ,  Cheng-Hung Wang

IPC: H01L21/74 ,  H01L23/535 ,  H01L27/12

CPC classification number: H01L27/1203 ,  H01L21/743 ,  H01L23/535

Abstract: Structures and methods for trench isolation are disclosed. In one example, a silicon-on-insulator (SOI) structure is disclosed. The SOI structure includes: a substrate, a dielectric layer and a polysilicon region. The substrate includes: a handle layer, an insulation layer arranged over the handle layer, a buried layer arranged over the insulation layer, and a trench extending downward from an upper surface of the buried layer and terminating in the handle layer. The dielectric layer is located on a bottom surface of the trench and contacting the handle layer. The polysilicon region is located in the trench and contacting the dielectric layer.

公开(公告)号：US11508628B2

公开(公告)日：2022-11-22

申请号：US17021727

申请日：2020-09-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Hung Wang ,  Tsung-Lin Lee ,  Wen-Chih Chiang ,  Kuan-Jung Chen

IPC: H01L21/8249 ,  H01L27/06 ,  H01L21/02 ,  H01L21/3065

Abstract: Disclosed is a method for forming a crystalline protective polysilicon layer which does not create defective voids during subsequent processes so as to provide effective protection to devices underneath. In one embodiment, a method for forming a semiconductor device, includes: depositing a protective coating on a first polysilicon layer; forming an epitaxial layer on the protective coating; and depositing a second polysilicon layer over the epitaxial layer, wherein the protective coating comprises a third polysilicon layer, wherein the third polysilicon layer is deposited at a first temperature in a range of 600-700 degree Celsius, and wherein the third polysilicon layer in the protect coating is configured to protect the first polysilicon layer when the second polysilicon layer is etched.

公开(公告)号：US11935795B2

公开(公告)日：2024-03-19

申请号：US17876442

申请日：2022-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Hung Wang ,  Tsung-Lin Lee ,  Wen-Chih Chiang ,  Kuan-Jung Chen

IPC: H01L21/8249 ,  H01L21/02 ,  H01L21/3065 ,  H01L27/06

CPC classification number: H01L21/8249 ,  H01L21/02164 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/3065 ,  H01L27/0623

Abstract: Disclosed is a method for forming a crystalline protective polysilicon layer which does not create defective voids during subsequent processes so as to provide effective protection to devices underneath. In one embodiment, a method for forming a semiconductor device, includes: depositing a protective coating on a first polysilicon layer; forming an epitaxial layer on the protective coating; and depositing a second polysilicon layer over the epitaxial layer, wherein the protective coating comprises a third polysilicon layer, wherein the third polysilicon layer is deposited at a first temperature in a range of 600-700 degree Celsius, and wherein the third polysilicon layer in the protect coating is configured to protect the first polysilicon layer when the second polysilicon layer is etched.

公开(公告)号：US11894381B2

公开(公告)日：2024-02-06

申请号：US16665791

申请日：2019-10-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Jung Chen ,  Tsung-Lin Lee ,  Chung-Ming Lin ,  Wen-Chih Chiang ,  Cheng-Hung Wang

IPC: H01L27/12 ,  H01L21/74 ,  H01L23/535

CPC classification number: H01L27/1203 ,  H01L21/743 ,  H01L23/535

Abstract: Structures and methods for trench isolation are disclosed. In one example, a silicon-on-insulator (SOI) structure is disclosed. The SOI structure includes: a substrate, a dielectric layer and a polysilicon region. The substrate includes: a handle layer, an insulation layer arranged over the handle layer, a buried layer arranged over the insulation layer, and a trench extending downward from an upper surface of the buried layer and terminating in the handle layer. The dielectric layer is located on a bottom surface of the trench and contacting the handle layer. The polysilicon region is located in the trench and contacting the dielectric layer.

公开(公告)号：US11031320B2

公开(公告)日：2021-06-08

申请号：US16675702

申请日：2019-11-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Jung Chen ,  Cheng-Hung Wang ,  Tsung-Lin Lee ,  Shiuan-Jeng Lin ,  Chun-Ming Lin ,  Wen-Chih Chiang

IPC: H01L23/48 ,  H01L23/532 ,  H01L23/58 ,  H01L21/02 ,  H01L29/06 ,  H01L21/311 ,  H01L21/768 ,  H01L23/528 ,  H01L21/762

Abstract: Structures and methods for reducing process charging damages are disclosed. In one example, a silicon-on-insulator (SOI) structure is disclosed. The SOI structure includes: a substrate, a polysilicon region and an etch stop layer. The substrate includes: a handle layer, an insulation layer arranged over the handle layer, and a buried layer arranged over the insulation layer. The polysilicon region extends downward from an upper surface of the buried layer and terminates in the handle layer. The etch stop layer is located on the substrate. The etch stop layer is in contact with both the substrate and the polysilicon region.

公开(公告)号：US20200176359A1

公开(公告)日：2020-06-04

申请号：US16675702

申请日：2019-11-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Jung Chen ,  Cheng-Hung Wang ,  Tsung-Lin Lee ,  Shiuan-Jeng Lin ,  Chun-Ming Lin ,  Wen-Chih Chiang

IPC: H01L23/48 ,  H01L23/532 ,  H01L23/58 ,  H01L21/02 ,  H01L21/762 ,  H01L21/311 ,  H01L21/768 ,  H01L23/528 ,  H01L29/06

Abstract: Structures and methods for reducing process charging damages are disclosed. In one example, a silicon-on-insulator (SOI) structure is disclosed. The SOI structure includes: a substrate, a polysilicon region and an etch stop layer. The substrate includes: a handle layer, an insulation layer arranged over the handle layer, and a buried layer arranged over the insulation layer. The polysilicon region extends downward from an upper surface of the buried layer and terminates in the handle layer. The etch stop layer is located on the substrate. The etch stop layer is in contact with both the substrate and the polysilicon region.

公开(公告)号：US20230282552A1

公开(公告)日：2023-09-07

申请号：US18196988

申请日：2023-05-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Jung CHEN ,  Cheng-Hung Wang ,  Tsung-Lin Lee ,  Shiuan-Jeng Lin ,  Chun-Ming Lin ,  Wen-Chih Chiang

IPC: H01L23/48 ,  H01L23/532 ,  H01L23/58 ,  H01L21/02 ,  H01L29/06 ,  H01L21/311 ,  H01L21/768 ,  H01L23/528 ,  H01L21/762

CPC classification number: H01L23/481 ,  H01L23/53271 ,  H01L23/53257 ,  H01L23/585 ,  H01L21/02532 ,  H01L29/0649 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/02595 ,  H01L23/528 ,  H01L21/76283

Abstract: Structures and methods for reducing process charging damages are disclosed. In one example, a silicon-on-insulator (SOI) structure is disclosed. The SOI structure includes: a substrate, a polysilicon region and an etch stop layer. The substrate includes: a handle layer, an insulation layer arranged over the handle layer, and a buried layer arranged over the insulation layer. The polysilicon region extends downward from an upper surface of the buried layer and terminates in the handle layer. The etch stop layer is located on the substrate. The etch stop layer is in contact with both the substrate and the polysilicon region.

公开(公告)号：US11688666B2

公开(公告)日：2023-06-27

申请号：US17336220

申请日：2021-06-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Jung Chen ,  Cheng-Hung Wang ,  Tsung-Lin Lee ,  Shiuan-Jeng Lin ,  Chun-Ming Lin ,  Wen-Chih Chiang

IPC: H01L23/48 ,  H01L23/532 ,  H01L23/58 ,  H01L21/02 ,  H01L29/06 ,  H01L21/311 ,  H01L21/768 ,  H01L23/528 ,  H01L21/762

CPC classification number: H01L23/481 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/31116 ,  H01L21/76283 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/528 ,  H01L23/53257 ,  H01L23/53271 ,  H01L23/585 ,  H01L29/0649

Abstract: Structures and methods for reducing process charging damages are disclosed. In one example, a silicon-on-insulator (SOI) structure is disclosed. The SOI structure includes: a substrate, a polysilicon region and an etch stop layer. The substrate includes: a handle layer, an insulation layer arranged over the handle layer, and a buried layer arranged over the insulation layer. The polysilicon region extends downward from an upper surface of the buried layer and terminates in the handle layer. The etch stop layer is located on the substrate. The etch stop layer is in contact with both the substrate and the polysilicon region.

公开(公告)号：US20210287963A1

公开(公告)日：2021-09-16

申请号：US17336220

申请日：2021-06-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Jung Chen ,  Cheng-Hung Wang ,  Tsung-Lin Lee ,  Shiuan-Jeng Lin ,  Chun-Ming Lin ,  Wen-Chih Chiang

IPC: H01L23/48 ,  H01L23/532 ,  H01L23/58 ,  H01L21/02 ,  H01L29/06 ,  H01L21/311 ,  H01L21/768 ,  H01L23/528 ,  H01L21/762

Abstract: Structures and methods for reducing process charging damages are disclosed. In one example, a silicon-on-insulator (SOI) structure is disclosed. The SOI structure includes: a substrate, a polysilicon region and an etch stop layer. The substrate includes: a handle layer, an insulation layer arranged over the handle layer, and a buried layer arranged over the insulation layer. The polysilicon region extends downward from an upper surface of the buried layer and terminates in the handle layer. The etch stop layer is located on the substrate. The etch stop layer is in contact with both the substrate and the polysilicon region.