公开(公告)号：US10008418B2

公开(公告)日：2018-06-26

申请号：US15282981

申请日：2016-09-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： De-Wei Yu ,  Chia-Ping Lo ,  Liang-Gi Yao ,  Weng Chang ,  Yee-Chia Yeo ,  Ziwei Fang

IPC: H01L29/66 ,  H01L21/3105 ,  H01L21/8238 ,  H01L21/336 ,  H01L21/324 ,  H01L21/02 ,  H01L21/268

CPC classification number: H01L21/823821 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/268 ,  H01L21/324 ,  H01L21/3247 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823828 ,  H01L21/823878 ,  H01L29/66545 ,  H01L29/66795

Abstract: A method of semiconductor device fabrication includes providing a substrate including a first fin element and a second fin element extending from the substrate. A first layer is formed over the first and second fin elements, where the first layer includes a gap. A laser anneal process is performed to the substrate to remove the gap in the first layer. An energy applied to the first layer during the laser anneal process is adjusted based on a height of the first layer.

公开(公告)号：US09231098B2

公开(公告)日：2016-01-05

申请号：US14067154

申请日：2013-10-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Tien-Chun Wang ,  Yi-Chun Lo ,  Chia-Der Chang ,  Guo-Chiang Chi ,  Chia-Ping Lo ,  Fu-Kai Yang ,  Hung-Chang Hsu ,  Mei-Yun Wang

IPC: H01L21/311 ,  H01L29/78 ,  H01L29/66 ,  H01L21/768 ,  H01L21/3115

CPC classification number: H01L29/665 ,  H01L21/26506 ,  H01L21/2658 ,  H01L21/26586 ,  H01L21/28518 ,  H01L21/3115 ,  H01L21/76802 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76897 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7834 ,  H01L29/7848

Abstract: Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a semiconductor substrate. A source region and a drain region are formed in the semiconductor substrate, and metal silicide regions are formed in the source region and the drain region, respectively. The semiconductor device further includes a metal gate stack formed over the semiconductor substrate and between the source region and the drain region. The semiconductor device also includes an insulating layer formed over the semiconductor substrate and surrounding the metal gate stack, wherein the insulating layer has contact openings exposing the metal silicide regions, respectively. The semiconductor device includes a dielectric spacer liner layer formed over inner walls of the contact openings, wherein the whole of the dielectric spacer liner layer is right above the metal silicide regions. The semiconductor device includes contact plugs formed in the contact openings.

Abstract translation: 提供了用于形成半导体器件的机构的实施例。 半导体器件包括半导体衬底。 在半导体衬底中形成源极区和漏极区，并且在源极区和漏极区分别形成金属硅化物区。 半导体器件还包括形成在半导体衬底上并且在源极区域和漏极区域之间的金属栅极叠层。 半导体器件还包括形成在半导体衬底上并围绕金属栅堆叠的绝缘层，其中绝缘层具有分别暴露金属硅化物区域的接触开口。 半导体器件包括在接触开口的内壁上形成的电介质隔离衬垫层，其中整个电介质隔离衬垫层位于金属硅化物区域的正上方。 半导体器件包括形成在接触开口中的接触插塞。

公开(公告)号：US09496367B2

公开(公告)日：2016-11-15

申请号：US14978167

申请日：2015-12-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tien-Chun Wang ,  Yi-Chun Lo ,  Chia-Der Chang ,  Guo-Chiang Chi ,  Chia-Ping Lo ,  Fu-Kai Yang ,  Hung-Chang Hsu ,  Mei-Yun Wang

IPC: H01L29/76 ,  H01L29/66 ,  H01L29/78 ,  H01L21/265 ,  H01L21/285 ,  H01L21/768 ,  H01L21/3115

CPC classification number: H01L29/665 ,  H01L21/26506 ,  H01L21/2658 ,  H01L21/26586 ,  H01L21/28518 ,  H01L21/3115 ,  H01L21/76802 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76897 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7834 ,  H01L29/7848

Abstract: A method for forming a semiconductor device is provided. The method includes providing a semiconductor substrate, a metal gate stack, and an insulating layer formed over the semiconductor substrate. A source region and a drain region are formed in the semiconductor substrate. The metal gate stack is between the source region and the drain region. The insulating layer surrounds the metal gate stack. The method includes forming contact openings passing through the insulating layer to expose the source region and the drain region, respectively. The method includes performing a first pre-amorphized implantation process to form amorphous regions in the source region and the drain region exposed by the contact openings. The method includes after the first pre-amorphized implantation process, forming a dielectric spacer liner layer over sidewalls of the contact openings. The dielectric spacer liner layer has holes exposing portions of the amorphous regions, respectively.

Abstract translation: 提供一种形成半导体器件的方法。 该方法包括提供半导体衬底，金属栅叠层和形成在半导体衬底上的绝缘层。 在半导体衬底中形成源极区和漏极区。 金属栅极堆叠在源极区域和漏极区域之间。 绝缘层围绕金属栅极叠层。 该方法包括形成通过绝缘层的接触开口，以分别暴露出源极区域和漏极区域。 该方法包括执行第一非淀粉化注入工艺以在源极区域和由接触开口暴露的漏极区域中形成非晶区域。 该方法包括在第一非淀粉植入工艺之后，在接触开口的侧壁上形成电介质隔离衬垫层。 电介质隔离衬垫层分别具有暴露非晶区域的部分的孔。