公开(公告)号：US20170062334A1

公开(公告)日：2017-03-02

申请号：US15350372

申请日：2016-11-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-I Yang ,  Chun-Yi Yang ,  Chih-Hao Lin ,  Hong-Seng Shue ,  Ruei-Hung Jang

IPC: H01L23/525 ,  H01L23/00

CPC classification number: H01L23/5256 ,  H01L23/5258 ,  H01L24/05 ,  H01L24/45 ,  H01L2224/04042 ,  H01L2224/05571 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/00 ,  H01L2224/45099

Abstract: The present disclosure relates to a semiconductor device. A fuse layer is arranged within a first dielectric layer. A bond pad is arranged on the first dielectric layer. A second dielectric layer is arranged along sidewall and upper surfaces of the bond pad. A passivation layer is arranged over the first and second dielectric layers, and the passivation layer having a bond pad opening overlying the bond pad and a fuse opening overlying the fuse layer. The bond pad has a bottom surface that is co-planar with a bottom surface of the passivation layer.

Abstract translation: 本公开涉及半导体器件。 熔丝层布置在第一介电层内。 接合焊盘设置在第一介电层上。 第二电介质层沿接合焊盘的侧壁和上表面布置。 钝化层布置在第一和第二电介质层上，并且钝化层具有覆盖接合焊盘的接合焊盘开口和覆盖熔丝层的保险丝开口。 接合焊盘具有与钝化层的底表面共面的底表面。

公开(公告)号：US11011462B2

公开(公告)日：2021-05-18

申请号：US15350372

申请日：2016-11-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-I Yang ,  Chun-Yi Yang ,  Chih-Hao Lin ,  Hong-Seng Shue ,  Ruei-Hung Jang

IPC: H01L23/62 ,  H01L23/525 ,  H01L23/00

Abstract: The present disclosure relates to a semiconductor device. A fuse layer is arranged within a first dielectric layer. A bond pad is arranged on the first dielectric layer. A second dielectric layer is arranged along sidewall and upper surfaces of the bond pad. A passivation layer is arranged over the first and second dielectric layers, and the passivation layer having a bond pad opening overlying the bond pad and a fuse opening overlying the fuse layer. The bond pad has a bottom surface that is co-planar with a bottom surface of the passivation layer.

公开(公告)号：US11011487B2

公开(公告)日：2021-05-18

申请号：US16908388

申请日：2020-06-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hao Lin ,  Chien-Kuo Chang ,  Tzu-Kai Lan ,  Chung-Chih Chen ,  Jr-Lin Hsu

IPC: H01L23/00 ,  H01L23/31

Abstract: A semiconductor package is provided, including a package component and a number of conductive connectors. The package component has a number of conductive features on a surface of the package component. The conductive connectors are formed on the conductive features of the package component. The conductive features include a first conductive feature and a second conductive feature contacting a first conductive connector and a second conductive connector, respectively. The size of the first conductive feature is smaller than the size of the second conductive feature, and the height of the first conductive connector on the first conductive feature is greater than the height of the second conductive connector on the second conductive feature.

公开(公告)号：US10700030B2

公开(公告)日：2020-06-30

申请号：US16258888

申请日：2019-01-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hao Lin ,  Chien-Kuo Chang ,  Tzu-Kai Lan ,  Chung-Chih Chen ,  Jr-Lin Hsu

IPC: H01L23/00 ,  H01L23/31

Abstract: A semiconductor package is provided, including a package substrate, a package component, and a number of conductive connectors. The package component has a number of conductive features on a first surface of the package component facing the package substrate. The conductive connectors electrically connect the conductive features of the package component to the package substrate. The conductive features include a first conductive feature and a second conductive feature contacting a first conductive connector and a second conductive connector, respectively. The size of the first conductive feature is smaller than the size of the second conductive feature, and the height of the first conductive connector on the first conductive feature is greater than the height of the second conductive connector on the second conductive feature.

公开(公告)号：US11088109B2

公开(公告)日：2021-08-10

申请号：US16679733

申请日：2019-11-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hao Lin ,  Chien-Kuo Chang ,  Pu-Sheng Lee ,  Fu-Jen Li ,  Hsien-Liang Meng

IPC: H01L23/31 ,  H01L23/367 ,  H01L23/373 ,  H01L23/498 ,  H01L21/48 ,  H01L25/00 ,  H01L25/065

Abstract: A package includes a die on a surface of a package component. The package also includes a first die stack on the surface of the package component. The package further includes a first thermal interface material (TIM) having a first thermal conductivity and disposed on the first die stack. In addition, the package includes a second thermal interface material (TIM) having a second thermal conductivity and disposed on the die. The first thermal conductivity of the first TIM is different from the second thermal conductivity of the second TIM.