公开(公告)号：US20220399272A1

公开(公告)日：2022-12-15

申请号：US17566564

申请日：2021-12-30

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yu-Tien SHEN ,  Ken-Hsien HSIEH ,  Shih-Ming CHANG

IPC分类号： H01L23/528 ,  H01L21/311 ,  H01L21/768

摘要： A semiconductor processing system includes a layout database that stores a plurality of layouts indicating features to be formed in a wafer. The semiconductor processing system includes a layout analyzer that analyzes the layouts and determines, for each layout, whether a non-perpendicular particle bombardment process should be utilized in conjunction with a photolithography process for forming the features of the layout in a wafer.

公开(公告)号：US20210096473A1

公开(公告)日：2021-04-01

申请号：US16587710

申请日：2019-09-30

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Ru-Gun LIU ,  Huicheng CHANG ,  Chia-Cheng CHEN ,  Jyu-Horng SHIEH ,  Liang-Yin CHEN ,  Shu-Huei SUEN ,  Wei-Liang LIN ,  Ya Hui CHANG ,  Yi-Nien SU ,  Yung-Sung YEN ,  Chia-Fong CHANG ,  Ya-Wen YEH ,  Yu-Tien SHEN

IPC分类号： G03F7/20 ,  H01L21/027

摘要： In a method of forming a pattern, a photo resist layer is formed over an underlying layer, the photo resist layer is exposed to an actinic radiation carrying pattern information, the exposed photo resist layer is developed to form a developed resist pattern, a directional etching operation is applied to the developed resist pattern to form a trimmed resist pattern, and the underlying layer is patterned using the trimmed resist pattern as an etching mask.

公开(公告)号：US20190164772A1

公开(公告)日：2019-05-30

申请号：US15967100

申请日：2018-04-30

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Chin-Yuan TSENG ,  Yu-Tien SHEN ,  Wei-Liang LIN ,  Chih-Ming LAI ,  Kuo-Cheng CHING ,  Shi Ning JU ,  Li-Te LIN ,  Ru-Gun LIU

IPC分类号： H01L21/311 ,  H01L21/32

摘要： A method of reducing corner rounding during patterning of a substrate to form a prescribed pattern comprising a corner includes dividing the pattern into a first pattern and a second pattern, the first pattern forming a first edge of the corner and the second pattern forming a second edge of the corner. At least a portion of the second pattern overlaps the first pattern such that the first edge intersects with the second edge to form a corner of the prescribed pattern. The method further includes forming the first pattern in a first mask layer disposed on a substrate to expose the substrate and forming the second pattern in the first mask layer to expose the substrate. The substrate exposed through the first mask layer is then etched to obtain the pattern.

公开(公告)号：US20220102139A1

公开(公告)日：2022-03-31

申请号：US17353400

申请日：2021-06-21

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chih-Kai YANG ,  Yu-Tien SHEN ,  Hsiang-Ming CHANG ,  Chun-Yen CHANG ,  Ya-Hui CHANG ,  Wei-Ting CHIEN ,  Chia-Cheng CHEN ,  Liang-Yin CHEN

IPC分类号： H01L21/027 ,  H01L21/311 ,  H01L21/768 ,  H01L21/3115 ,  G03F7/20

摘要： A semiconductor process system includes an ion source configured to bombard with a photoresist structure on a wafer. The semiconductor process system reduces a width of the photoresist structure by bombarding the photoresist structure with ions in multiple distinct ion bombardment steps having different characteristics.

公开(公告)号：US20200006085A1

公开(公告)日：2020-01-02

申请号：US16383539

申请日：2019-04-12

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Ya-Wen YEH ,  Yu-Tien SHEN ,  Shih-Chun HUANG ,  Po-Chin CHANG ,  Wei-Liang LIN ,  Yung-Sung YEN ,  Wei-Hao WU ,  Li-Te LIN ,  Pinyen LIN ,  Ru-Gun LIU

IPC分类号： H01L21/3213 ,  H01L21/66

摘要： In a method of manufacturing a semiconductor device, an underlying structure is formed over a substrate. A film is formed over the underlying structure. Surface topography of the film is measured and the surface topography is stored as topography data. A local etching is performed by using directional etching and scanning the substrate so that an entire surface of the film is subjected to the directional etching. A plasma beam intensity of the directional etching is adjusted according to the topography data.

公开(公告)号：US20200335340A1

公开(公告)日：2020-10-22

申请号：US16921032

申请日：2020-07-06

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Shih-Chun HUANG ,  Chiu-Hsiang CHEN ,  Ya-Wen YEH ,  Yu-Tien SHEN ,  Po-Chin CHANG ,  Chien Wen LAI ,  Wei-Liang LIN ,  Ya Hui CHANG ,  Yung-Sung YEN ,  Li-Te LIN ,  Pinyen LIN ,  Ru-Gun LIU ,  Chin-Hsiang LIN

IPC分类号： H01L21/033 ,  H01L21/027 ,  H01L21/311 ,  H01L21/02 ,  H01L21/265

摘要： A method of manufacturing a semiconductor device including operations of forming a first hard mask over an underlying layer on a substrate by a photolithographic and etching method, forming a sidewall spacer pattern having a first sidewall portion and a second sidewall portion on opposing sides of the first hard mask, etching the first sidewall portion, etching the first hard mask and leaving the second sidewall portion bridging a gap of the etched first hard mask, and processing the underlying layer using the second hard mask.

公开(公告)号：US20230386834A1

公开(公告)日：2023-11-30

申请号：US18447869

申请日：2023-08-10

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chih-Kai YANG ,  Yu-Tien SHEN ,  Hsiang-Ming CHANG ,  Chun-Yen CHANG ,  Ya-Hui CHANG ,  Wei-Ting CHIEN ,  Chia-Cheng CHEN ,  Liang-Yin CHEN

IPC分类号： H01L21/027 ,  H01L21/311 ,  G03F7/00 ,  H01L21/3115 ,  H01L21/768

CPC分类号： H01L21/0273 ,  H01L21/31144 ,  G03F7/70058 ,  H01L21/31155 ,  H01L21/76877

摘要： A semiconductor process system includes an ion source configured to bombard with a photoresist structure on a wafer. The semiconductor process system reduces a width of the photoresist structure by bombarding the photoresist structure with ions in multiple distinct ion bombardment steps having different characteristics.

公开(公告)号：US20220357669A1

公开(公告)日：2022-11-10

申请号：US17566563

申请日：2021-12-30

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shih-Ming CHANG ,  Ken-Hsien HSIEH ,  Yu-Tien SHEN

IPC分类号： G03F7/20 ,  G06F30/398 ,  G03F1/22

摘要： A semiconductor processing system includes a first photolithography system and a second photolithography system. The semiconductor processing system includes a layout database that stores a plurality of layouts indicating features to be formed in a wafer. The semiconductor processing system includes a layout analyzer that analyzes the layouts and selects either the first photolithography system or the second photolithography system based on dimensions of features in the layouts.

公开(公告)号：US20190341254A1

公开(公告)日：2019-11-07

申请号：US16512336

申请日：2019-07-15

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Shih-Chun HUANG ,  Chin-Hsiang LIN ,  Chien-Wen LAI ,  Ru-Gun LIU ,  Wei-Liang LIN ,  Ya Hui CHANG ,  Yung-Sung YEN ,  Yu-Tien SHEN ,  Ya-Wen YEH

IPC分类号： H01L21/033 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/3105

摘要： A method of fabricating a semiconductor device includes forming a hard mask layer over a substrate. A multi-layer resist is formed over the hard mask layer. The multi-layer resist is etched to form a plurality of openings in the multi-layer resist to expose a portion of the hard mask layer. Ion are directionally provided at an angle to the multi-layer resist to predominately contact sidewalls of the plurality of openings in the multi-layer resist rather than the hard mask layer. In one embodiment, the multi-layer resist is directionally etched by directing etch ions at an angle to predominately contact sidewalls of the plurality of openings in the multi-layer resist rather than the hard mask layer. In another embodiment, the multi-layer resist is directionally implanted by directing implant ions at an angle to predominately contact sidewalls of the plurality of openings in the multi-layer resist rather than the hard mask layer.