公开(公告)号：US11287746B1

公开(公告)日：2022-03-29

申请号：US17197707

申请日：2021-03-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Chung Chien ,  Hao-Ken Hung ,  Chih-Chieh Yang ,  Ming-Feng Shieh ,  Chun-Ming Hu

IPC: G03F7/20

Abstract: Semiconductor processing apparatuses and methods are provided in which a semiconductor wafer is flipped and then rotated between patterning of front and back sides of the semiconductor wafer by first and second reticles, respectively. In some embodiments, a method includes patterning, by a first reticle, a first layer on a first side of a semiconductor wafer while the first side of the semiconductor wafer is facing a first direction. The semiconductor wafer is then flipped. A second side of the semiconductor wafer that is opposite the first side faces the first direction after the flipping the semiconductor wafer. The semiconductor wafer is then rotated about a rotational axis extending along the first direction, and a second layer on the second side of the semiconductor wafer is patterned by a second reticle.

公开(公告)号：US20190258179A1

公开(公告)日：2019-08-22

申请号：US16402828

申请日：2019-05-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Weimin Hu ,  Yang-Hung Chang ,  Kai-Hsiung Chen ,  Chun-Ming Hu ,  Chih-Ming Ke

IPC: G03F7/20

Abstract: The present disclosure provides a method. The method includes patterning a substrate by a patterning tool; collecting a plurality of overlay errors from a plurality of fields on the substrate; identifying noise from the plurality of overlay errors by applying a first filtering operation and a second filtering operation that is different from the first filtering operation. The method further includes grouping the plurality of overlay errors that are not identified as noise into a set of filtered overlay errors; calculating an overlay compensation based on the set of filtered overlay errors; and performing a compensation process to the patterning tool according to the overlay compensation.

公开(公告)号：US10281827B2

公开(公告)日：2019-05-07

申请号：US15644126

申请日：2017-07-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Weimin Hu ,  Yang-Hung Chang ,  Kai-Hsiung Chen ,  Chun-Ming Hu ,  Chih-Ming Ke

IPC: G03F7/20

Abstract: The present disclosure provides a method. The method includes patterning a substrate by a patterning tool; collecting a plurality of overlay errors from a plurality of fields on the substrate; identifying noise from the plurality of overlay errors by applying a first filtering operation and a second filtering operation that is different from the first filtering operation. The method further includes grouping the plurality of overlay errors that are not identified as noise into a set of filtered overlay errors; calculating an overlay compensation based on the set of filtered overlay errors; and performing a compensation process to the patterning tool according to the overlay compensation.

公开(公告)号：US10684556B2

公开(公告)日：2020-06-16

申请号：US16402828

申请日：2019-05-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Weimin Hu ,  Yang-Hung Chang ,  Kai-Hsiung Chen ,  Chun-Ming Hu ,  Chih-Ming Ke

IPC: G03F7/20

Abstract: The present disclosure provides a method. The method includes patterning a substrate by a patterning tool; collecting a plurality of overlay errors from a plurality of fields on the substrate; identifying noise from the plurality of overlay errors by applying a first filtering operation and a second filtering operation that is different from the first filtering operation. The method further includes grouping the plurality of overlay errors that are not identified as noise into a set of filtered overlay errors; calculating an overlay compensation based on the set of filtered overlay errors; and performing a compensation process to the patterning tool according to the overlay compensation.

公开(公告)号：US10521548B2

公开(公告)日：2019-12-31

申请号：US16042468

申请日：2018-07-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yang-Hung Chang ,  Che-Yuan Sun ,  Chih-Ming Ke ,  Chun-Ming Hu

IPC: G06F17/50 ,  G01R31/28 ,  G01R31/307 ,  G06T7/00

Abstract: Defect information obtained from a test wafer is received. The test wafer was fabricated according to an Integrated Circuit (IC) design layout. A plurality of first regions of interest (ROIs) is received based on the defect information. The first ROIs each correspond to a region of the IC design layout where a wafer defect has occurred. A frequency domain analysis is performed for the first ROIs. A wafer defect probability is forecast for the IC design layout based at least in part on the frequency domain analysis.

公开(公告)号：US20180173110A1

公开(公告)日：2018-06-21

申请号：US15644126

申请日：2017-07-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Weimin Hu ,  Yang-Hung Chang ,  Kai-Hsiung Chen ,  Chun-Ming Hu ,  Chih-Ming Ke

IPC: G03F7/20

CPC classification number: G03F7/70633 ,  G03F7/705

Abstract: The present disclosure provides a method. The method includes patterning a substrate by a patterning tool; collecting a plurality of overlay errors from a plurality of fields on the substrate; identifying noise from the plurality of overlay errors by applying a first filtering operation and a second filtering operation that is different from the first filtering operation. The method further includes grouping the plurality of overlay errors that are not identified as noise into a set of filtered overlay errors; calculating an overlay compensation based on the set of filtered overlay errors; and performing a compensation process to the patterning tool according to the overlay compensation.

公开(公告)号：US11513444B2

公开(公告)日：2022-11-29

申请号：US16901278

申请日：2020-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Weimin Hu ,  Yang-Hung Chang ,  Kai-Hsiung Chen ,  Chun-Ming Hu ,  Chih-Ming Ke

IPC: G03F7/20

Abstract: The present disclosure provides a system. The system includes a metrology tool configured to collect overlay errors from a patterned substrate; and a controller module coupled to the metrology tool and configured to generate an overlay compensation from the collected overlay errors, wherein the generating of the overlay compensation includes identifying a portion of the overlay errors as a set of outliers, identifying inside the set of outliers overlay errors not due to reticle effects, thereby creating a set of noise, excluding the set of noise from overlay errors, thereby creating a set of filtered overlay errors, and calculating the overlay compensation based on the set of filtered overlay errors.

公开(公告)号：US20200310255A1

公开(公告)日：2020-10-01

申请号：US16901278

申请日：2020-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Weimin Hu ,  Yang-Hung Chang ,  Kai-Hsiung Chen ,  Chun-Ming Hu ,  Chih-Ming Ke

IPC: G03F7/20

Abstract: The present disclosure provides a system. The system includes a metrology tool configured to collect overlay errors from a patterned substrate; and a controller module coupled to the metrology tool and configured to generate an overlay compensation from the collected overlay errors, wherein the generating of the overlay compensation includes identifying a portion of the overlay errors as a set of outliers, identifying inside the set of outliers overlay errors not due to reticle effects, thereby creating a set of noise, excluding the set of noise from overlay errors, thereby creating a set of filtered overlay errors, and calculating the overlay compensation based on the set of filtered overlay errors.

公开(公告)号：US20180330040A1

公开(公告)日：2018-11-15

申请号：US16042468

申请日：2018-07-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yang-Hung Chang ,  Che-Yuan Sun ,  Chih-Ming Ke ,  Chun-Ming Hu

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G01R31/287 ,  G01R31/2894 ,  G01R31/307 ,  G06T7/0004 ,  G06T2207/20056 ,  G06T2207/30148

Abstract: Defect information obtained from a test wafer is received. The test wafer was fabricated according to an Integrated Circuit (IC) design layout. A plurality of first regions of interest (ROIs) is received based on the defect information. The first ROIs each correspond to a region of the IC design layout where a wafer defect has occurred. A frequency domain analysis is performed for the first ROIs. A wafer defect probability is forecast for the IC design layout based at least in part on the frequency domain analysis.

公开(公告)号：US10031997B1

公开(公告)日：2018-07-24

申请号：US15386818

申请日：2016-12-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yang-Hung Chang ,  Che-Yuan Sun ,  Chih-Ming Ke ,  Chun-Ming Hu

IPC: G06F17/50

Abstract: Defect information obtained from a test wafer is received. The test wafer was fabricated according to an Integrated. Circuit (IC) design layout. A plurality of first regions of interest (ROIs) is received based on the defect information. The first ROIs each correspond to a region of the IC design layout where a wafer defect has occurred. A frequency domain analysis is performed for the first ROIs. A wafer defect probability is forecast for the IC design layout based at least in part on the frequency domain analysis.