公开(公告)号：US11665897B2

公开(公告)日：2023-05-30

申请号：US17694320

申请日：2022-03-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Chang Wu ,  Chihy-Yuan Cheng ,  Sz-Fan Chen ,  Shun-Shing Yang ,  Wei-Lin Chang ,  Ching-Sen Kuo ,  Feng-Jia Shiu ,  Chun-Chang Chen

IPC: H01L27/11546 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/027 ,  H01L27/11521 ,  H01L29/66 ,  H01L29/423 ,  H01L23/544 ,  H01L27/11524 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L27/11546 ,  H01L21/0276 ,  H01L21/31058 ,  H01L21/31111 ,  H01L21/31144 ,  H01L23/544 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/42324 ,  H01L29/6656 ,  H01L29/66825 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/517 ,  H01L2223/5442 ,  H01L2223/54426

Abstract: A wafer having a first region and a second region is provided. A first topography variation exists between the first region and the second region. A first layer is formed over the first region and over the second region of the wafer. The first layer is patterned. A patterned first layer causes a second topography variation to exist between the first region and the second region. The second topography variation is smoother than the first topography variation. A second layer is formed over the first region and the second region. At least a portion of the second layer is formed over the patterned first layer.

公开(公告)号：US20220199636A1

公开(公告)日：2022-06-23

申请号：US17694320

申请日：2022-03-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Chang Wu ,  Chihy-Yuan Cheng ,  Sz-Fan Chen ,  Shun-Shing Yang ,  Wei-Lin Chang ,  Ching-Sen Kuo ,  Feng-Jia Shiu ,  Chun-Chang Chen

IPC: H01L27/11546 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/027 ,  H01L27/11521 ,  H01L29/66 ,  H01L29/423 ,  H01L23/544 ,  H01L27/11524

Abstract: A wafer having a first region and a second region is provided. A first topography variation exists between the first region and the second region. A first layer is formed over the first region and over the second region of the wafer. The first layer is patterned. A patterned first layer causes a second topography variation to exist between the first region and the second region. The second topography variation is smoother than the first topography variation. A second layer is formed over the first region and the second region. At least a portion of the second layer is formed over the patterned first layer.

公开(公告)号：US10522557B2

公开(公告)日：2019-12-31

申请号：US15796992

申请日：2017-10-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Chang Wu ,  Chihy-Yuan Cheng ,  Sz-Fan Chen ,  Shun-Shing Yang ,  Wei-Lin Chang ,  Ching-Sen Kuo ,  Feng-Jia Shiu ,  Chun-Chang Chen

IPC: H01L27/11546 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/027 ,  H01L27/11521 ,  H01L29/66 ,  H01L29/423 ,  H01L23/544 ,  H01L27/11524 ,  H01L29/49 ,  H01L29/51

Abstract: A wafer having a first region and a second region is provided. A first topography variation exists between the first region and the second region. A first layer is formed over the first region and over the second region of the wafer. The first layer is patterned. A patterned first layer causes a second topography variation to exist between the first region and the second region. The second topography variation is smoother than the first topography variation. A second layer is formed over the first region and the second region. At least a portion of the second layer is formed over the patterned first layer.

公开(公告)号：US20190131313A1

公开(公告)日：2019-05-02

申请号：US15796992

申请日：2017-10-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Chang Wu ,  Chihy-Yuan Cheng ,  Sz-Fan Chen ,  Shun-Shing Yang ,  Wei-Lin Chang ,  Ching-Sen Kuo ,  Feng-Jia Shiu ,  Chun-Chang Chen

IPC: H01L27/11546 ,  H01L29/66 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/027 ,  H01L27/11521 ,  H01L29/423 ,  H01L23/544

Abstract: A wafer having a first region and a second region is provided. A first topography variation exists between the first region and the second region. A first layer is formed over the first region and over the second region of the wafer. The first layer is patterned. A patterned first layer causes a second topography variation to exist between the first region and the second region. The second topography variation is smoother than the first topography variation. A second layer is formed over the first region and the second region. At least a portion of the second layer is formed over the patterned first layer.

公开(公告)号：US11769662B2

公开(公告)日：2023-09-26

申请号：US17206908

申请日：2021-03-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Lin Chang ,  Chih-Chien Wang ,  Chihy-Yuan Cheng ,  Sz-Fan Chen ,  Chien-Hung Lin ,  Chun-Chang Chen ,  Ching-Sen Kuo ,  Feng-Jia Shiu

IPC: H01L21/02 ,  H01L21/027

CPC classification number: H01L21/0206 ,  H01L21/0277

Abstract: Embodiments are directed to a method for minimizing electrostatic charges in a semiconductor substrate. The method includes depositing photoresist on a semiconductor substrate to form a photoresist layer on the semiconductor substrate. The photoresist layer is exposed to radiation. The photoresist layer is developed using a developer solution. The semiconductor substrate is cleaned with a first cleaning liquid to wash the developer solution from the photoresist layer. A tetramethylammonium hydroxide (TMAH) solution is applied to the semiconductor substrate to reduce charges accumulated in the semiconductor substrate.

公开(公告)号：US11362038B2

公开(公告)日：2022-06-14

申请号：US17062677

申请日：2020-10-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yeong-Jyh Lin ,  Ching I Li ,  De-Yang Chiou ,  Sz-Fan Chen ,  Han-Jui Hu ,  Ching-Hung Wang ,  Ru-Liang Lee ,  Chung-Yi Yu

IPC: H01L23/544 ,  H01L21/027 ,  H01L21/683 ,  G03F1/42 ,  G03F1/70 ,  H01L21/66

Abstract: Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure. The method includes forming a plurality of upper alignment marks on a semiconductor wafer. A plurality of lower alignment marks is formed on a handle wafer and correspond to the upper alignment marks. The semiconductor wafer is bonded to the handle wafer such that centers of the upper alignment marks are laterally offset from centers of corresponding lower alignment marks. An overlay (OVL) shift is measured between the handle wafer and the semiconductor wafer by detecting the plurality of upper alignment marks and the plurality of lower alignment marks. A photolithography process is performed by a photolithography tool to partially form an integrated circuit (IC) structure over the semiconductor wafer. During the photolithography process the photolithography tool is compensatively aligned according to the OVL shift.

公开(公告)号：US11276699B2

公开(公告)日：2022-03-15

申请号：US16721565

申请日：2019-12-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Chang Wu ,  Chihy-Yuan Cheng ,  Sz-Fan Chen ,  Shun-Shing Yang ,  Wei-Lin Chang ,  Ching-Sen Kuo ,  Feng-Jia Shiu ,  Chun-Chang Chen

IPC: H01L27/11529 ,  H01L27/11546 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/027 ,  H01L27/11521 ,  H01L29/66 ,  H01L29/423 ,  H01L23/544 ,  H01L27/11524 ,  H01L29/49 ,  H01L29/51

Abstract: A wafer having a first region and a second region is provided. A first topography variation exists between the first region and the second region. A first layer is formed over the first region and over the second region of the wafer. The first layer is patterned. A patterned first layer causes a second topography variation to exist between the first region and the second region. The second topography variation is smoother than the first topography variation. A second layer is formed over the first region and the second region. At least a portion of the second layer is formed over the patterned first layer.

公开(公告)号：US20210375781A1

公开(公告)日：2021-12-02

申请号：US17062677

申请日：2020-10-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yeong-Jyh Lin ,  Ching I Li ,  De-Yang Chiou ,  Sz-Fan Chen ,  Han-Jui Hu ,  Ching-Hung Wang ,  Ru-Liang Lee ,  Chung-Yi Yu

IPC: H01L23/544 ,  H01L21/027 ,  H01L21/683 ,  H01L21/66 ,  G03F1/42 ,  G03F1/70

Abstract: Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure. The method includes forming a plurality of upper alignment marks on a semiconductor wafer. A plurality of lower alignment marks is formed on a handle wafer and correspond to the upper alignment marks. The semiconductor wafer is bonded to the handle wafer such that centers of the upper alignment marks are laterally offset from centers of corresponding lower alignment marks. An overlay (OVL) shift is measured between the handle wafer and the semiconductor wafer by detecting the plurality of upper alignment marks and the plurality of lower alignment marks. A photolithography process is performed by a photolithography tool to partially form an integrated circuit (IC) structure over the semiconductor wafer. During the photolithography process the photolithography tool is compensatively aligned according to the OVL shift.