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    3D image profiling techniques for lithography
    1.
    发明授权
    3D image profiling techniques for lithography 有权
    用于光刻的3D图像分析技术

    公开(公告)号：US08952329B1

    公开(公告)日：2015-02-10

    申请号：US14045138

    申请日：2013-10-03

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： I-Chang Shih ,  Yi-Jie Chen ,  Chia-Cheng Chang ,  Feng-Yuan Chiu ,  Ying-Chou Cheng ,  Chiu Hsiu Chen ,  Bing-Syun Yeh ,  Ru-Gun Liu

    IPC分类号： G01N23/00 ,  G21K7/00 ,  G01B15/04

    CPC分类号： H01L22/12 ,  G01B2210/56 ,  G03F7/70433 ,  G03F7/705

    摘要： A method for characterizing a three-dimensional surface profile of a semiconductor workpiece is provided. In this method, the three-dimensional surface profile is imaged from a normal angle to measure widths of various surfaces in a first image. The three-dimensional surface is also imaged from a first oblique angle to re-measure the widths of the various surfaces in a second image. Based on differences in widths of corresponding surfaces for first and second images, a feature height and sidewall angle are determined for the three-dimensional profile.

    摘要翻译： 提供了一种用于表征半导体工件的三维表面轮廓的方法。 在该方法中，从正常角度对三维表面轮廓进行成像，以测量第一图像中的各种表面的宽度。 三维表面也从第一倾斜角度成像，以重新测量第二图像中各种表面的宽度。 基于第一和第二图像的相应表面的宽度差异，确定三维轮廓的特征高度和侧壁角度。

    Model based simulation method with fast bias contour for lithography process check
    2.
    发明授权
    Model based simulation method with fast bias contour for lithography process check 有权
    基于模型的模拟方法，具有快速偏置轮廓的光刻过程检查

    公开(公告)号：US08910092B1

    公开(公告)日：2014-12-09

    申请号：US14078729

    申请日：2013-11-13

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： I-Chang Shih ,  Feng-Yuan Chiu ,  Ying-Chou Cheng ,  Chiu Hsiu Chen ,  Ru-Gun Liu

    IPC分类号： G06F17/50

    CPC分类号： G03F1/36

    摘要： Integrated circuit design techniques are disclosed. In some methods, a target layout design having a geometric pattern thereon is received. A set of fast-bias contour (FBC) rules is applied to the target layout design to provide an electronic photomask having FBC-edits. The FBC-edits differentiate the electronic photomask from the target layout design, and the FBC rules are applied without previously applying optical proximity correction (OPC) to the target layout design. A lithography process check is performed on the electronic photomask to determine whether a patterned integrated circuit layer, which is to be manufactured based on the electronic photomask, is expected to be in conformance with the geometric pattern of the target layout design.

    摘要翻译： 公开了集成电路设计技术。 在一些方法中，接收其上具有几何图案的目标布局设计。 将一组快速偏置轮廓（FBC）规则应用于目标布局设计，以提供具有FBC编辑的电子光掩模。 FBC编辑将电子光掩模与目标布局设计区分开来，并且在不预先将光学邻近校正（OPC）应用于目标布局设计的情况下应用FBC规则。 对电子光掩模进行光刻处理检查，以确定是否将基于电子光掩模制造的图案化集成电路层是否符合目标布局设计的几何图案。