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    Method of forming trenches with different depths
    1.
    发明授权
    Method of forming trenches with different depths 有权

    公开(公告)号：US11348830B2

    公开(公告)日：2022-05-31

    申请号：US17114174

    申请日：2020-12-07

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chao-Hsun Wang ,  Hsien-Cheng Wang ,  Mei-Yun Wang

    IPC: H01L21/768 ,  H01L21/311 ,  H01L29/43 ,  H01L29/08 ,  H01L21/8234 ,  H01L29/40 ,  H01L23/485

    Abstract: A semiconductor device includes a gate structure disposed over a substrate, and a first dielectric layer disposed over the substrate, including and over the gate structure. A first metal feature is disposed in the first dielectric layer, including an upper portion having a first width and a lower portion having a second width that is different than the first width. A dielectric spacer is disposed along the lower portion of the first metal feature, wherein the upper portion of the first metal feature is disposed over the dielectric spacer. A second dielectric layer is disposed over the first dielectric layer, including over the first metal feature and a second metal feature extends through the second dielectric layer to physically contact with the first metal feature. A third metal feature extends through the second dielectric layer and the first dielectric layer to physically contact the gate structure.

    Method of Forming Trenches with Different Depths
    2.
    发明申请
    Method of Forming Trenches with Different Depths 有权

    公开(公告)号：US20220293461A1

    公开(公告)日：2022-09-15

    申请号：US17827480

    申请日：2022-05-27

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chao-Hsun Wang ,  Hsien-Cheng Wang ,  Mei-Yun Wang

    IPC: H01L21/768 ,  H01L21/311 ,  H01L21/8234 ,  H01L23/485 ,  H01L29/08 ,  H01L29/40 ,  H01L29/43

    Abstract: A semiconductor device includes a gate structure disposed over a substrate, and a first dielectric layer disposed over the substrate, including and over the gate structure. A first metal feature is disposed in the first dielectric layer, including an upper portion having a first width and a lower portion having a second width that is different than the first width. A dielectric spacer is disposed along the lower portion of the first metal feature, wherein the upper portion of the first metal feature is disposed over the dielectric spacer. A second dielectric layer is disposed over the first dielectric layer, including over the first metal feature and a second metal feature extends through the second dielectric layer to physically contact with the first metal feature. A third metal feature extends through the second dielectric layer and the first dielectric layer to physically contact the gate structure.

    Mechanisms for semiconductor device structure
    3.
    发明授权
    Mechanisms for semiconductor device structure 有权
    半导体器件结构的机理

    公开(公告)号：US09425048B2

    公开(公告)日：2016-08-23

    申请号：US14073408

    申请日：2013-11-06

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Hsin-Ying Lin ,  Mei-Yun Wang ,  Hsien-Cheng Wang ,  Fu-Kai Yang ,  Shih-Wen Liu ,  Audrey Hsiao-Chiu Hsu

    IPC: H01L21/033 ,  H01L29/40 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66

    CPC classification number: H01L21/28123 ,  H01L21/0334 ,  H01L21/76805 ,  H01L21/76897 ,  H01L29/402 ,  H01L29/42376 ,  H01L29/4983 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659

    Abstract: Embodiments of mechanisms of a semiconductor device structure are provided. The semiconductor device structure includes a substrate and a metal gate structure formed over the substrate. The semiconductor device structure further includes a funnel shaped hard mask structure formed over the metal gate structure. Formation of voids, which tend to be formed in a rectangular hard mask structure, is prevented. In addition, formation of a self-aligned contact in the semiconductor device becomes easier, and risks of shortage between the contact and a metal gate structure in the semiconductor device decreased. In addition, a method for forming the semiconductor device structure is also provided. The method may include a gate last process.

    Abstract translation: 提供半导体器件结构的机构的实施例。 半导体器件结构包括在衬底上形成的衬底和金属栅极结构。 半导体器件结构还包括形成在金属栅极结构上的漏斗形硬掩模结构。 容易形成矩形硬掩模结构的空隙的形成被防止。 此外，半导体器件中的自对准接触的形成变得容易，并且半导体器件中的接触和金属栅极结构之间的短缺的风险降低。 此外，还提供了一种用于形成半导体器件结构的方法。 该方法可以包括门最后进程。

    Integrated circuit structure with thinned contact
    4.
    发明授权
    Integrated circuit structure with thinned contact 有权
    具有减薄接触的集成电路结构

    公开(公告)号：US09312259B2

    公开(公告)日：2016-04-12

    申请号：US14073365

    申请日：2013-11-06

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

    Inventor： Hsin-Ying Lin ,  Mei-Yun Wang ,  Hsien-Cheng Wang ,  Shih-Wen Liu ,  Fu-Kai Yang ,  Audrey Hsiao-Chiu Hsu

    IPC: H01L29/76 ,  H01L27/088 ,  H01L21/8234

    CPC classification number: H01L21/76816 ,  H01L21/76877 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823871 ,  H01L27/088

    Abstract: Embodiments of mechanism for an integrated circuit (IC) structure are provided. The IC structure includes a substrate including a first diffusion region, a second diffusion region, and an isolation structure separating the first diffusion region and the second diffusion region. The IC structure further includes a gate structure formed over the substrate, and the gate structure extends from the first diffusion region to the second diffusion region. The IC structure further includes a contact formed over the substrate, and the contact includes a wide portion over the first diffusion region and the second diffusion region and a thin portion over the isolation structure.

    Abstract translation: 提供了一种用于集成电路（IC）结构的机构的实施例。 IC结构包括：基板，包括第一扩散区域，第二扩散区域以及分离第一扩散区域和第二扩散区域的隔离结构。 IC结构还包括形成在衬底上的栅极结构，并且栅极结构从第一扩散区延伸到第二扩散区。 IC结构还包括形成在衬底上的触点，并且触点包括在第一扩散区域和第二扩散区域上的宽部分以及隔离结构上的薄部分。

    Method for forming integrated circuit structure with thinned contact
    7.
    发明授权
    Method for forming integrated circuit structure with thinned contact 有权
    用薄型接触形成集成电路结构的方法

    公开(公告)号：US09576847B2

    公开(公告)日：2017-02-21

    申请号：US15081334

    申请日：2016-03-25

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Hsin-Ying Lin ,  Mei-Yun Wang ,  Hsien-Cheng Wang ,  Shih-Wen Liu ,  Fu-Kai Yang ,  Audrey Hsiao-Chiu Hsu

    IPC: H01L21/336 ,  H01L21/768 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/8238

    CPC classification number: H01L21/76816 ,  H01L21/76877 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823871 ,  H01L27/088

    Abstract: Methods for forming integrated circuit structures are provided. The method includes providing a substrate including a first diffusion region, a second diffusion region, and an isolation structure separating the first diffusion region and the second diffusion region. The method further includes forming a gate structure over the substrate and forming an inter-layer dielectric (ILD) layer over the substrate. The method further includes forming a cutting mask over a portion of the gate structure over the isolation structure, and the cutting mask has an extending portion covering a portion of the ILD layer. The method further includes forming a photoresist layer having an opening, and a portion of the extending portion of the cutting mask is exposed by the opening. The method further includes etching the ILD layer through the opening to form a trench and filling the trench with a conductive material to form a contact.

    Abstract translation: 提供了形成集成电路结构的方法。 该方法包括提供包括第一扩散区，第二扩散区和分离第一扩散区和第二扩散区的隔离结构的衬底。 该方法还包括在衬底上形成栅极结构并在衬底上形成层间电介质（ILD）层。 该方法还包括在隔离结构上的栅极结构的一部分上形成切割掩模，并且切割掩模具有覆盖ILD层的一部分的延伸部分。 所述方法还包括形成具有开口的光致抗蚀剂层，并且所述切割掩模的所述延伸部分的一部分被所述开口暴露。 该方法还包括通过开口蚀刻ILD层以形成沟槽并用导电材料填充沟槽以形成接触。

    Method of Forming Trenches with Different Depths
    9.
    发明申请
    Method of Forming Trenches with Different Depths 审中-公开

    公开(公告)号：US20190259657A1

    公开(公告)日：2019-08-22

    申请号：US16403921

    申请日：2019-05-06

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chao-Hsun Wang ,  Hsien-Cheng Wang ,  Mei-Yun Wang

    IPC: H01L21/768 ,  H01L23/485 ,  H01L29/08 ,  H01L29/40 ,  H01L21/311 ,  H01L29/43 ,  H01L21/8234

    Abstract: A semiconductor device includes a gate structure disposed over a substrate, and a first dielectric layer disposed over the substrate, including and over the gate structure. A first metal feature is disposed in the first dielectric layer, including an upper portion having a first width and a lower portion having a second width that is different than the first width. A dielectric spacer is disposed along the lower portion of the first metal feature, wherein the upper portion of the first metal feature is disposed over the dielectric spacer. A second dielectric layer is disposed over the first dielectric layer, including over the first metal feature and a second metal feature extends through the second dielectric layer to physically contact with the first metal feature. A third metal feature extends through the second dielectric layer and the first dielectric layer to physically contact the gate structure.

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