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    Designed-based interconnect structure in semiconductor structure
    3.
    发明授权
    Designed-based interconnect structure in semiconductor structure 有权
    半导体结构中基于设计的互连结构

    公开(公告)号：US09281273B1

    公开(公告)日：2016-03-08

    申请号：US14476349

    申请日：2014-09-03

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

    Inventor： Chih-Liang Chen ,  Chih-Ming Lai ,  Yung-Sung Yen ,  Kam-Tou Sio ,  Tsong-Hua Ou ,  Chun-Kuang Chen ,  Ru-Gun Liu ,  Shu-Hui Sung ,  Charles Chew-Yuen Young

    IPC: H01L27/118 ,  H01L23/528 ,  H01L23/522

    CPC classification number: H01L23/528 ,  H01L23/5226 ,  H01L27/0207 ,  H01L27/11803 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Semiconductor structures are provided. The semiconductor structure includes a plurality of gate structures extending in a first direction formed over a substrate and a contact formed adjacent to the gate structures over the substrate. The semiconductor structure further includes a plurality of metal layers formed over the gate structures. In addition, some of the metal layers include metal lines extending in the first direction, and some of the metal layers include metal lines extending in a second direction substantially perpendicular to the first direction. Furthermore, the gate structures follow the following equation: 0.2 ⁢ ⁢ P gate ⁢ ⁢ min + 0.35 ⁢ ⁢ L gate ⁢ ⁢ min + 0.3 ⁢ ⁢ H gate ⁢ ⁢ min - 20 0.2 ⁢ ⁢ L gate ⁢ ⁢ min + 0.8 ⁢ ⁢ H gate ⁢ ⁢ min - 5 × 0.3 ⁢ ⁢ L gate ⁢ ⁢ min + 0.3 ⁢ ⁢ H gate ⁢ ⁢ min + 5 38 ≤ 0.32 Pgate min is the minimum value among gate pitches of the gate structures. Lgate min is the minimum value among gate lengths of the gate structures. Hgate min is the minimum value among gate heights of the gate structures.

    Abstract translation: 提供半导体结构。 半导体结构包括沿着形成在衬底上的第一方向延伸的多个栅极结构以及与衬底上的栅极结构相邻形成的触点。 半导体结构还包括形成在栅极结构上的多个金属层。 此外，一些金属层包括在第一方向上延伸的金属线，并且一些金属层包括沿基本上垂直于第一方向的第二方向延伸的金属线。 此外，门结构遵循以下公式：0.2⁢P gate⁢⁢min⁢⁢⁢⁢⁢⁢⁢min min min min⁢⁢⁢⁢⁢⁢⁢⁢⁢⁢⁢⁢⁢⁢ H门槛最小 - 5×0.3⁢L门⁢最小+ 0.3⁢H门⁢最小+ 5 38≤0.32 P门min是门结构的栅间距中的最小值。 Lgate min是门结构的栅极长度之间的最小值。 Hgate min是门结构栅极高度的最小值。

    Multi-patterning conflict free integrated circuit design
    6.
    发明授权
    Multi-patterning conflict free integrated circuit design 有权
    多模式无冲突集成电路设计

    公开(公告)号：US09026971B1

    公开(公告)日：2015-05-05

    申请号：US14148898

    申请日：2014-01-07

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chien Lin Ho ,  Chin-Chang Hsu ,  Hung Lung Lin ,  Wen-Ju Yang ,  Yi-Kan Cheng ,  Tsong-Hua Ou ,  Wen-Li Cheng ,  Ken-Hsien Hsieh ,  Ching Hsiang Chang ,  Ting Yu Chen ,  Li-Chun Tien

    IPC: G06F17/50

    CPC classification number: G06F17/5081 ,  G03F7/70466 ,  G06F17/5072 ,  G06F2217/12 ,  Y02P90/265

    Abstract: The present disclosure relates to a method and apparatus for forming a multiple patterning lithograph (MPL) compliant integrated circuit layout by operating a construction validation check on unassembled IC cells to enforce design restrictions that prevent MPL conflicts after assembly. In some embodiments, the method is performed by generating a plurality of unassembled integrated circuit (IC) cells having a multiple patterning design layer. A construction validation check is performed on the unassembled IC cells to identify violating IC cells having shapes disposed in patterns comprising potential multiple patterning coloring conflicts. Design shapes within a violating IC cell are adjusted to achieve a plurality of violation free IC cells. The plurality of violation free IC cells are then assembled to form an MPL compliant IC layout. Since the MPL compliant IC layout is free of coloring conflicts, a decomposition algorithm can be operated without performing a post assembly color conflict check.

    Abstract translation: 本发明涉及一种用于通过对未组装的IC单元进行构造验证检查以形成在组装之后防止MPL冲突的设计限制来形成多重图案化平版印刷术（MPL）兼容集成电路布局的方法和装置。 在一些实施例中，该方法通过产生具有多个图案化设计层的多个未组装的集成电路（IC）单元来执行。 在未组装的IC细胞上进行结构验证检查，以识别具有以包含潜在的多个图案化着色冲突的图案布置的形状的违反IC细胞。 调整违规IC单元内的设计形状，以实现多个无冲突的IC单元。 然后组合多个违规免费IC电池以形成符合MPL的IC布局。 由于MPL兼容IC布局没有着色冲突，因此可以在不执行后期组合颜色冲突检查的情况下操作分解算法。

    Layout method and system for multi-patterning integrated circuits
    9.
    发明授权
    Layout method and system for multi-patterning integrated circuits 有权
    多图案集成电路的布局方法和系统

    公开(公告)号：US09262577B2

    公开(公告)日：2016-02-16

    申请号：US14267013

    申请日：2014-05-01

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Huang-Yu Chen ,  Tsong-Hua Ou ,  Ken-Hsien Hsieh ,  Chin-Hsiung Hsu

    IPC: G06F17/50

    CPC classification number: G06F17/5081 ,  G06F17/5072 ,  G06F2217/12

    Abstract: A method identifies, as an independent node, any node representing a circuit pattern in any odd loop of a layout of a region of a layer of an IC that is not included in any other odd loop of the layout. The layer is to have a plurality of circuit patterns to be patterned using at least three photomasks. The method identifies, as a safe independent node, any independent node not closer than a threshold distance from any other independent nodes in another odd loop of the layout. The layout is modified, if the circuit patterns in the layout include any odd loop without any safe independent node, so that that after the modifying, each odd loop has at least one safe independent node.

    Abstract translation: 一种方法将作为独立节点的任何节点表示在不包括在布局的任何其它奇数循环中的IC层的区域的布局的任何奇数循环中的电路图案。 该层将具有使用至少三个光掩模进行图案化的多个电路图案。 该方法将安全独立节点识别为距离布局的另一个奇数循环中任何其他独立节点不超过阈值距离的任何独立节点。 布局被修改，如果布局中的电路图案包括没有任何安全独立节点的任何奇数循环，使得在修改之后，每个奇数循环至少有一个安全独立节点。

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