公开(公告)号：US10749004B2

公开(公告)日：2020-08-18

申请号：US16009925

申请日：2018-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jyh-nan Lin ,  Ding-I Liu ,  Yuh-Ta Fan

IPC: H01L29/12 ,  H01L21/00 ,  H01L29/26 ,  H01L21/02 ,  H01L21/768 ,  H01L23/532

Abstract: A semiconductor device includes a metal layer, an insulating layer disposed above the metal layer, and a multi-layer diffusion barrier disposed on the metal layer between the metal layer and the insulating layer. The multi-layer diffusion barrier includes a first material layer including a metallic nitride and a second material layer including a metallic oxide.

公开(公告)号：US11742393B2

公开(公告)日：2023-08-29

申请号：US17683749

申请日：2022-03-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jyh-nan Lin ,  Ding-I Liu ,  Yuh-Ta Fan

IPC: H01L29/26 ,  H01L21/02 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L29/26 ,  H01L21/02172 ,  H01L21/02436 ,  H01L21/7685 ,  H01L21/76826 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76855 ,  H01L23/53295

Abstract: A semiconductor device includes a metal layer, an insulating layer disposed above the metal layer, and a multi-layer diffusion barrier disposed on the metal layer between the metal layer and the insulating layer. The multi-layer diffusion barrier includes a first material layer including a metallic nitride and a second material layer including a metallic oxide.

公开(公告)号：US20190006474A1

公开(公告)日：2019-01-03

申请号：US16009925

申请日：2018-06-15

Applicant: Taiwan Semiconductor Manufacturing Co, Ltd

Inventor： Jyh-nan Lin ,  Ding-I Liu ,  Yuh-Ta Fan

IPC: H01L29/26 ,  H01L21/02 ,  H01L21/768

Abstract: A semiconductor device includes a metal layer, an insulating layer disposed above the metal layer, and a multi-layer diffusion barrier disposed on the metal layer between the metal layer and the insulating layer. The multi-layer diffusion barrier includes a first material layer including a metallic nitride and a second material layer including a metallic oxide.

公开(公告)号：US11264467B2

公开(公告)日：2022-03-01

申请号：US16985276

申请日：2020-08-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jyh-nan Lin ,  Ding-I Liu ,  Yuh-Ta Fan

IPC: H01L29/12 ,  H01L21/00 ,  H01L29/26 ,  H01L21/02 ,  H01L21/768 ,  H01L23/532

Abstract: A semiconductor device includes a metal layer, an insulating layer disposed above the metal layer, and a multi-layer diffusion barrier disposed on the metal layer between the metal layer and the insulating layer. The multi-layer diffusion barrier includes a first material layer including a metallic nitride and a second material layer including a metallic oxide.

公开(公告)号：US10978337B2

公开(公告)日：2021-04-13

申请号：US16550901

申请日：2019-08-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jyh-nan Lin ,  Mu-Min Hung ,  Kai-Shiung Hsu ,  Ding-I Liu

IPC: H01L21/768 ,  H01L23/522 ,  H01L21/02 ,  C23C16/455 ,  C23C16/34

Abstract: Aluminum-containing layers and systems and methods for forming the same are provided. In an embodiment, a method includes depositing an aluminum-containing layer on a substrate in a chamber by atomic layer deposition. The depositing further includes contacting the substrate with an aluminum-containing precursor in a first pulse having a first peak pulse flow rate and a first pulse width; contacting the substrate with a nitrogen-containing precursor; contacting the substrate with the aluminum-containing precursor in a second pulse having a second peak pulse flow rate and a second pulse width; and contacting the substrate with the nitrogen-containing precursor. The first peak pulse flow rate is greater than the second peak pulse flow rate. The first pulse width is smaller than the second pulse width.

公开(公告)号：US11264273B2

公开(公告)日：2022-03-01

申请号：US16941040

申请日：2020-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Jen Chen ,  Kai-Shiung Hsu ,  Ding-I Liu ,  Jyh-nan Lin

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: A method for improving reliability of interconnect structures for semiconductor devices is disclosed. The method includes forming a contact structure on a transistor and forming a metallization layer on the contact structure. The forming the metallization layer includes depositing an inter-metal dielectric (IMD) layer on the transistor, forming an opening within the IMD layer to expose a top surface of the contact structure, depositing a metallic layer to fill the opening, forming an electron barrier layer within the IMD layer, and forming a capping layer within the metallic layer. The electron barrier layer has a hole carrier concentration higher than a hole carrier concentration of a portion of the IMD layer underlying the electron barrier layer. The capping layer has a hole carrier concentration higher than a hole carrier concentration of a portion of the metallic layer underlying the capping layer.

公开(公告)号：US20210233805A1

公开(公告)日：2021-07-29

申请号：US16941040

申请日：2020-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Jen CHEN ,  Kai-Shiung Hsu ,  Ding-I Liu ,  Jyh-nan Lin

IPC: H01L21/768 ,  H01L23/522

Abstract: A method for improving reliability of interconnect structures for semiconductor devices is disclosed. The method includes forming a contact structure on a transistor and forming a metallization layer on the contact structure. The forming the metallization layer includes depositing an inter-metal dielectric (IMD) layer on the transistor, forming an opening within the IMD layer to expose a top surface of the contact structure, depositing a metallic layer to fill the opening, forming an electron barrier layer within the IMD layer, and forming a capping layer within the metallic layer. The electron barrier layer has a hole carrier concentration higher than a hole carrier concentration of a portion of the IMD layer underlying the electron barrier layer. The capping layer has a hole carrier concentration higher than a hole carrier concentration of a portion of the metallic layer underlying the capping layer.

公开(公告)号：US20230377955A1

公开(公告)日：2023-11-23

申请号：US18227726

申请日：2023-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Jen CHEN ,  Kai-Shiung Hsu ,  Ding-I Liu ,  Jyh-nan Lin

IPC: H01L21/768 ,  H01L23/522

CPC classification number: H01L21/76826 ,  H01L23/5226 ,  H01L21/76849 ,  H01L21/76834 ,  H01L21/76832 ,  H01L23/53295

Abstract: A method for improving reliability of interconnect structures for semiconductor devices is disclosed. The method includes forming a contact structure on a transistor and forming a metallization layer on the contact structure. The forming the metallization layer includes depositing an inter-metal dielectric (IMD) layer on the transistor, forming an opening within the IMD layer to expose a top surface of the contact structure, depositing a metallic layer to fill the opening, forming an electron barrier layer within the IMD layer, and forming a capping layer within the metallic layer. The electron barrier layer has a hole carrier concentration higher than a hole carrier concentration of a portion of the IMD layer underlying the electron barrier layer. The capping layer has a hole carrier concentration higher than a hole carrier concentration of a portion of the metallic layer underlying the capping layer.

公开(公告)号：US20220181203A1

公开(公告)日：2022-06-09

申请号：US17682823

申请日：2022-02-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Jen Chen ,  Kai-Shiung Hsu ,  Ding-I Liu ,  Jyh-nan Lin

IPC: H01L21/768 ,  H01L23/522

Abstract: A method for improving reliability of interconnect structures for semiconductor devices is disclosed. The method includes forming a contact structure on a transistor and forming a metallization layer on the contact structure. The forming the metallization layer includes depositing an inter-metal dielectric (IMD) layer on the transistor, forming an opening within the IMD layer to expose a top surface of the contact structure, depositing a metallic layer to fill the opening, forming an electron barrier layer within the IMD layer, and forming a capping layer within the metallic layer. The electron barrier layer has a hole carrier concentration higher than a hole carrier concentration of a portion of the IMD layer underlying the electron barrier layer. The capping layer has a hole carrier concentration higher than a hole carrier concentration of a portion of the metallic layer underlying the capping layer.