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    Cut Metal Gate Refill With Buffer Layer
    1.
    发明申请
    Cut Metal Gate Refill With Buffer Layer 有权

    公开(公告)号：US20250014946A1

    公开(公告)日：2025-01-09

    申请号：US18348967

    申请日：2023-07-07

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Fan Hsuan Chien ,  Su-Yu Yeh ,  Teng-Ta Hung ,  Chun-Jen Chen ,  Pei Yen Cheng ,  Shih-Chi Lin

    IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/78

    Abstract: A method includes etching a gate stack to form a trench extending through the gate stack, the gate stack including a metal gate electrode and a gate dielectric, wherein forming the trench removes a portion of the gate stack to separate the gate stack into a first gate stack portion and a second gate stack portion; extending the trench through an isolation region under the gate stack and into a semiconductor substrate under the isolation region; conformally depositing a first dielectric material on surfaces in the trench; and depositing a second dielectric material on the first dielectric material to fill the trench, wherein the first dielectric material is a more flexible material than the second dielectric material.

    ELECTRON MIGRATION CONTROL IN INTERCONNECT STRUCTURES
    2.
    发明申请
    ELECTRON MIGRATION CONTROL IN INTERCONNECT STRUCTURES 有权

    公开(公告)号：US20220181203A1

    公开(公告)日：2022-06-09

    申请号：US17682823

    申请日：2022-02-28

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chun-Jen Chen ,  Kai-Shiung Hsu ,  Ding-I Liu ,  Jyh-nan Lin

    IPC: H01L21/768 ,  H01L23/522

    Abstract: A method for improving reliability of interconnect structures for semiconductor devices is disclosed. The method includes forming a contact structure on a transistor and forming a metallization layer on the contact structure. The forming the metallization layer includes depositing an inter-metal dielectric (IMD) layer on the transistor, forming an opening within the IMD layer to expose a top surface of the contact structure, depositing a metallic layer to fill the opening, forming an electron barrier layer within the IMD layer, and forming a capping layer within the metallic layer. The electron barrier layer has a hole carrier concentration higher than a hole carrier concentration of a portion of the IMD layer underlying the electron barrier layer. The capping layer has a hole carrier concentration higher than a hole carrier concentration of a portion of the metallic layer underlying the capping layer.

    Image process method to improve mask inspection performance
    4.
    发明授权
    Image process method to improve mask inspection performance 有权
    图像处理方法提高掩模检查性能

    公开(公告)号：US09529255B2

    公开(公告)日：2016-12-27

    申请号：US14096167

    申请日：2013-12-04

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Meng-Lin Lu ,  Ching-Ting Yang ,  Chun-Jen Chen ,  Chien-Hung Lai ,  Jong-Yuh Chang

    IPC: G06F17/50 ,  G03F1/84

    CPC classification number: G03F1/84

    Abstract: The present disclosure relates to a method of inspecting a photomask to decrease false defects, which uses a plurality of image rendering models with varying emphasis on different design aspects, and an associated apparatus. In some embodiments, the method is performed by forming an integrated circuit (IC) design comprising a graphical representation of an integrated circuit. A first image rendering simulation is performed on the IC design using an initial image rendering model to determine a plurality of initial mask defects. A second image rendering simulation is performed on the IC design using a modified image rendering model that emphasizes a design aspect to determine a plurality of modified mask defects. By comparing the plurality of initial mask defects with the plurality of modified mask defects, falsely identified mask defects can be detected and eliminated.

    Abstract translation: 本公开涉及一种检查光掩模以减少错误缺陷的方法，其使用多个不同强调不同设计方面的图像渲染模型以及相关联的装置。 在一些实施例中，该方法通过形成包括集成电路的图形表示的集成电路（IC）设计来执行。 使用初始图像渲染模型对IC设计执行第一图像渲染模拟以确定多个初始掩模缺陷。 使用强调设计方面以确定多个修改的掩模缺陷的修改的图像渲染模型对IC设计执行第二图像渲染模拟。 通过将多个初始掩模缺陷与多个修改的掩模缺陷进行比较，可以检测和消除错误识别的掩模缺陷。

    Electron migration control in interconnect structures
    5.
    发明授权
    Electron migration control in interconnect structures 有权

    公开(公告)号：US11264273B2

    公开(公告)日：2022-03-01

    申请号：US16941040

    申请日：2020-07-28

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chun-Jen Chen ,  Kai-Shiung Hsu ,  Ding-I Liu ,  Jyh-nan Lin

    IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

    Abstract: A method for improving reliability of interconnect structures for semiconductor devices is disclosed. The method includes forming a contact structure on a transistor and forming a metallization layer on the contact structure. The forming the metallization layer includes depositing an inter-metal dielectric (IMD) layer on the transistor, forming an opening within the IMD layer to expose a top surface of the contact structure, depositing a metallic layer to fill the opening, forming an electron barrier layer within the IMD layer, and forming a capping layer within the metallic layer. The electron barrier layer has a hole carrier concentration higher than a hole carrier concentration of a portion of the IMD layer underlying the electron barrier layer. The capping layer has a hole carrier concentration higher than a hole carrier concentration of a portion of the metallic layer underlying the capping layer.

    Method for forming bump structure
    6.
    发明授权
    Method for forming bump structure 有权

    公开(公告)号：US11145613B2

    公开(公告)日：2021-10-12

    申请号：US16124337

    申请日：2018-09-07

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Li-Guo Lee ,  Yung-Sheng Liu ,  Yi-Chen Liu ,  Yi-Jen Lai ,  Chun-Jen Chen ,  Hsi-Kuei Cheng

    IPC: H01L23/00

    Abstract: Methods for forming semiconductor structures are provided. The method for forming a semiconductor structure includes forming a metal pad over a first substrate and forming a resist layer having an opening over the metal layer. The method for forming a semiconductor structure further includes forming a conductive pillar and a solder layer over the conductive pillar in the opening of the resist layer and removing the resist layer. The method for forming a semiconductor structure further includes removing a portion of the conductive pillar so that the conductive pillar has an angled sidewall.

    Semiconductor Device Structure and Manufacturing Method
    7.
    发明申请
    Semiconductor Device Structure and Manufacturing Method 审中-公开

    公开(公告)号：US20190131264A1

    公开(公告)日：2019-05-02

    申请号：US16219453

    申请日：2018-12-13

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Li-Guo Lee ,  Yung-Sheng Liu ,  Yi-Chen Liu ,  Yi-Jen Lai ,  Chun-Jen Chen ,  Hsi-Kuei Cheng

    IPC: H01L23/00

    Abstract: A semiconductor device structure and a manufacturing method are provided. The semiconductor device structure includes a semiconductor substrate and a dielectric layer over the semiconductor substrate. The semiconductor device structure also includes a conductive trace over the dielectric layer. The semiconductor device structure further includes a conductive feature over the conductive trace, and a width of the conductive feature is substantially equal to or larger than a maximum width of the conductive trace. In addition, the semiconductor device structure includes a conductive bump over the conductive feature.

    Semiconductor device structure and manufacturing method
    8.
    发明授权
    Semiconductor device structure and manufacturing method 有权

    公开(公告)号：US10163843B2

    公开(公告)日：2018-12-25

    申请号：US15795547

    申请日：2017-10-27

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Li-Guo Lee ,  Yung-Sheng Liu ,  Yi-Chen Liu ,  Yi-Jen Lai ,  Chun-Jen Chen ,  Hsi-Kuei Cheng

    IPC: H01L23/00

    Abstract: A semiconductor device structure and a manufacturing method are provided. The semiconductor device structure includes a semiconductor substrate and a dielectric layer over the semiconductor substrate. The semiconductor device structure also includes a conductive trace over the dielectric layer. The semiconductor device structure further includes a conductive feature over the conductive trace, and a width of the conductive feature is substantially equal to or larger than a maximum width of the conductive trace. In addition, the semiconductor device structure includes a conductive bump over the conductive feature.

    Semiconductor device structure and manufacturing method
    10.
    发明授权
    Semiconductor device structure and manufacturing method 有权

    公开(公告)号：US11217548B2

    公开(公告)日：2022-01-04

    申请号：US16219453

    申请日：2018-12-13

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Li-Guo Lee ,  Yung-Sheng Liu ,  Yi-Chen Liu ,  Yi-Jen Lai ,  Chun-Jen Chen ,  Hsi-Kuei Cheng

    IPC: H01L23/00

    Abstract: A semiconductor device structure and a manufacturing method are provided. The semiconductor device structure includes a semiconductor substrate and a dielectric layer over the semiconductor substrate. The semiconductor device structure also includes a conductive trace over the dielectric layer. The semiconductor device structure further includes a conductive feature over the conductive trace, and a width of the conductive feature is substantially equal to or larger than a maximum width of the conductive trace. In addition, the semiconductor device structure includes a conductive bump over the conductive feature.

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