公开(公告)号：US10818790B2

公开(公告)日：2020-10-27

申请号：US16435070

申请日：2019-06-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Fen Chen ,  Chui-Ya Peng ,  Ching Yu ,  Pin-Hen Lin ,  Yen Chuang ,  Yuh-Ta Fan

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L29/165

Abstract: A semiconductor device includes a gate stack over a semiconductor substrate. A spacer extends substantially along a first sidewall of the gate stack. An epitaxy structure is in the semiconductor substrate. A liner wraps around the epitaxy structure and has an outer surface in contact with the semiconductor substrate and an inner surface facing the epitaxy structure. The outer surface of the liner has a first facet extending upwards and towards the gate stack from a bottom of the first liner and a second facet extending upwards and towards an outer sidewall of the spacer from a top of the first facet to a top of the liner, such that a corner is formed between the first facet and the second facet, and the inner surface of the first liner defines a first curved corner pointing towards the corner formed between the first facet and the second facet.

公开(公告)号：US10749004B2

公开(公告)日：2020-08-18

申请号：US16009925

申请日：2018-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jyh-nan Lin ,  Ding-I Liu ,  Yuh-Ta Fan

IPC: H01L29/12 ,  H01L21/00 ,  H01L29/26 ,  H01L21/02 ,  H01L21/768 ,  H01L23/532

Abstract: A semiconductor device includes a metal layer, an insulating layer disposed above the metal layer, and a multi-layer diffusion barrier disposed on the metal layer between the metal layer and the insulating layer. The multi-layer diffusion barrier includes a first material layer including a metallic nitride and a second material layer including a metallic oxide.

公开(公告)号：US11411108B2

公开(公告)日：2022-08-09

申请号：US17078856

申请日：2020-10-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Fen Chen ,  Chui-Ya Peng ,  Ching Yu ,  Pin-Hen Lin ,  Yen Chuang ,  Yuh-Ta Fan

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L29/165

Abstract: A semiconductor device includes a gate stack over a semiconductor substrate. A spacer extends along a first sidewall of the gate stack. An epitaxy structure is in the semiconductor substrate. A liner wraps around the epitaxy structure and has an outer surface in contact with the semiconductor substrate and an inner surface facing the epitaxy structure. The outer surface of the liner has a first facet extending upwards and towards the gate stack from a bottom of the first liner and a second facet extending upwards and towards an outer sidewall of the spacer from a top of the first facet to a top of the liner, such that a corner is formed between the first facet and the second facet, and the inner surface of the first liner defines a first curved corner pointing towards the corner formed between the first facet and the second facet.

公开(公告)号：US10153156B2

公开(公告)日：2018-12-11

申请号：US15433739

申请日：2017-02-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun Hsiung Tsai ,  Kuo-Feng Yu ,  Yuh-Ta Fan

IPC: H01L21/02 ,  C23C16/455 ,  C23C16/52 ,  C23C16/44

Abstract: According to one example, a process includes performing a first plurality of layer deposition cycles of a deposition process on a substrate, and after performing the first plurality of layer deposition cycles, performing a plasma enhanced layer deposition cycle comprising a plasma treatment process. The first plurality of layer deposition cycles are performed without a plasma treatment process.

公开(公告)号：US11742393B2

公开(公告)日：2023-08-29

申请号：US17683749

申请日：2022-03-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jyh-nan Lin ,  Ding-I Liu ,  Yuh-Ta Fan

IPC: H01L29/26 ,  H01L21/02 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L29/26 ,  H01L21/02172 ,  H01L21/02436 ,  H01L21/7685 ,  H01L21/76826 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76855 ,  H01L23/53295

Abstract: A semiconductor device includes a metal layer, an insulating layer disposed above the metal layer, and a multi-layer diffusion barrier disposed on the metal layer between the metal layer and the insulating layer. The multi-layer diffusion barrier includes a first material layer including a metallic nitride and a second material layer including a metallic oxide.

公开(公告)号：US20220190122A1

公开(公告)日：2022-06-16

申请号：US17683749

申请日：2022-03-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jyh-nan LIN ,  Ding-I Liu ,  Yuh-Ta Fan

IPC: H01L29/26 ,  H01L21/02 ,  H01L21/768 ,  H01L23/532

Abstract: A semiconductor device includes a metal layer, an insulating layer disposed above the metal layer, and a multi-layer diffusion barrier disposed on the metal layer between the metal layer and the insulating layer. The multi-layer diffusion barrier includes a first material layer including a metallic nitride and a second material layer including a metallic oxide.

公开(公告)号：US20190006474A1

公开(公告)日：2019-01-03

申请号：US16009925

申请日：2018-06-15

Applicant: Taiwan Semiconductor Manufacturing Co, Ltd

Inventor： Jyh-nan Lin ,  Ding-I Liu ,  Yuh-Ta Fan

IPC: H01L29/26 ,  H01L21/02 ,  H01L21/768

Abstract: A semiconductor device includes a metal layer, an insulating layer disposed above the metal layer, and a multi-layer diffusion barrier disposed on the metal layer between the metal layer and the insulating layer. The multi-layer diffusion barrier includes a first material layer including a metallic nitride and a second material layer including a metallic oxide.

公开(公告)号：US12033900B2

公开(公告)日：2024-07-09

申请号：US17815094

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chandrashekhar Prakash Savant ,  Chia-Ming Tsai ,  Yuh-Ta Fan ,  Tien-Wei Yu

IPC: H01L21/8238 ,  H01L21/28 ,  H01L21/3213 ,  H01L27/092 ,  H01L29/49

CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L21/28123 ,  H01L21/32134 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/4966

Abstract: The present disclosure describes a semiconductor device having metal boundary trench isolation with electrically conductive intermediate structures acting as a metal diffusion barrier. The semiconductor structure includes a first fin structure and a second fin structure on a substrate, an insulating layer between the first and second fin structures, a gate dielectric layer on the insulating layer and the first and second fin structures, and a first work function stack and a second work function stack on the gate dielectric layer. The first work function stack is over the first fin structure and a first portion of the insulating layer, and the second work function stack is over the second fin structure and a second portion of the insulating layer adjacent to the first portion. The semiconductor structure further includes a conductive intermediate structure on the gate dielectric layer and between the first and second work function stacks.

公开(公告)号：US11430700B2

公开(公告)日：2022-08-30

申请号：US16913429

申请日：2020-06-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chandrashekhar Prakash Savant ,  Chia-Ming Tsai ,  Yuh-Ta Fan ,  Tien-Wei Yu

IPC: H01L21/8238 ,  H01L21/28 ,  H01L21/3213 ,  H01L27/092 ,  H01L29/49

Abstract: The present disclosure describes a semiconductor device having metal boundary trench isolation with electrically conductive intermediate structures acting as a metal diffusion barrier. The semiconductor structure includes a first fin structure and a second fin structure on a substrate, an insulating layer between the first and second fin structures, a gate dielectric layer on the insulating layer and the first and second fin structures, and a first work function stack and a second work function stack on the gate dielectric layer. The first work function stack is over the first fin structure and a first portion of the insulating layer, and the second work function stack is over the second fin structure and a second portion of the insulating layer adjacent to the first portion. The semiconductor structure further includes a conductive intermediate structure on the gate dielectric layer and between the first and second work function stacks.

公开(公告)号：US10319857B2

公开(公告)日：2019-06-11

申请号：US15796853

申请日：2017-10-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Fen Chen ,  Chui-Ya Peng ,  Ching Yu ,  Pin-Hen Lin ,  Yen Chuang ,  Yuh-Ta Fan

IPC: H01L29/08 ,  H01L29/66 ,  H01L29/78 ,  H01L29/165

Abstract: A semiconductor device includes a substrate, a liner, and an epitaxy structure. The substrate has a recess. The liner is disposed in the recess. The liner is denser than the substrate. The epitaxy structure is disposed in the recess. The liner is disposed between the epitaxy structure and the substrate.