公开(公告)号：US20150262951A1

公开(公告)日：2015-09-17

申请号：US14208744

申请日：2014-03-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Li-Guo LEE ,  Yung-Sheng LIU ,  Yi-Chen LIU ,  Yi-Jen LAI ,  Chun-Jen CHEN ,  Hsi-Kuei CHENG

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/81 ,  H01L2224/0345 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05147 ,  H01L2224/05184 ,  H01L2224/05556 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11831 ,  H01L2224/13007 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13021 ,  H01L2224/13023 ,  H01L2224/13076 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2924/13091 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor structure is provided. The semiconductor structure includes a first substrate and a metal pad formed over the first substrate. The semiconductor structure further includes a modified conductive pillar having a top portion and a bottom portion formed over the metal pad and a solder layer formed over the modified conductive pillar. In addition, the top portion of the modified conductive pillar has a first sidewall in a first direction and a bottom portion of the modified conductive pillar has a second sidewall in a second direction different from the first direction.

Abstract translation: 提供半导体结构。 半导体结构包括形成在第一衬底上的第一衬底和金属衬垫。 该半导体结构还包括一个改进的导电柱，其具有形成在金属焊盘上的顶部和底部，以及形成在改性的导电柱上的焊料层。 此外，改性导电柱的顶部具有在第一方向上的第一侧壁，并且改性导电柱的底部在不同于第一方向的第二方向上具有第二侧壁。

公开(公告)号：US20230377955A1

公开(公告)日：2023-11-23

申请号：US18227726

申请日：2023-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Jen CHEN ,  Kai-Shiung Hsu ,  Ding-I Liu ,  Jyh-nan Lin

IPC: H01L21/768 ,  H01L23/522

CPC classification number: H01L21/76826 ,  H01L23/5226 ,  H01L21/76849 ,  H01L21/76834 ,  H01L21/76832 ,  H01L23/53295

Abstract: A method for improving reliability of interconnect structures for semiconductor devices is disclosed. The method includes forming a contact structure on a transistor and forming a metallization layer on the contact structure. The forming the metallization layer includes depositing an inter-metal dielectric (IMD) layer on the transistor, forming an opening within the IMD layer to expose a top surface of the contact structure, depositing a metallic layer to fill the opening, forming an electron barrier layer within the IMD layer, and forming a capping layer within the metallic layer. The electron barrier layer has a hole carrier concentration higher than a hole carrier concentration of a portion of the IMD layer underlying the electron barrier layer. The capping layer has a hole carrier concentration higher than a hole carrier concentration of a portion of the metallic layer underlying the capping layer.

公开(公告)号：US20190019772A1

公开(公告)日：2019-01-17

申请号：US16124337

申请日：2018-09-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Guo LEE ,  Yung-Sheng LIU ,  Yi-Chen LIU ,  Yi-Jen LAI ,  Chun-Jen CHEN ,  Hsi-Kuei CHENG

IPC: H01L23/00

Abstract: Methods for forming semiconductor structures are provided. The method for forming a semiconductor structure includes forming a metal pad over a first substrate and forming a resist layer having an opening over the metal layer. The method for forming a semiconductor structure further includes forming a conductive pillar and a solder layer over the conductive pillar in the opening of the resist layer and removing the resist layer. The method for forming a semiconductor structure further includes removing a portion of the conductive pillar so that the conductive pillar has an angled sidewall.

公开(公告)号：US20210233805A1

公开(公告)日：2021-07-29

申请号：US16941040

申请日：2020-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Jen CHEN ,  Kai-Shiung Hsu ,  Ding-I Liu ,  Jyh-nan Lin

IPC: H01L21/768 ,  H01L23/522

Abstract: A method for improving reliability of interconnect structures for semiconductor devices is disclosed. The method includes forming a contact structure on a transistor and forming a metallization layer on the contact structure. The forming the metallization layer includes depositing an inter-metal dielectric (IMD) layer on the transistor, forming an opening within the IMD layer to expose a top surface of the contact structure, depositing a metallic layer to fill the opening, forming an electron barrier layer within the IMD layer, and forming a capping layer within the metallic layer. The electron barrier layer has a hole carrier concentration higher than a hole carrier concentration of a portion of the IMD layer underlying the electron barrier layer. The capping layer has a hole carrier concentration higher than a hole carrier concentration of a portion of the metallic layer underlying the capping layer.

公开(公告)号：US20150262952A1

公开(公告)日：2015-09-17

申请号：US14208871

申请日：2014-03-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Li-Guo LEE ,  Yi-Chen LIU ,  Yung-Sheng LIU ,  Yi-Jen LAI ,  Chun-Jen CHEN ,  Hsi-Kuei CHENG

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/81 ,  H01L2224/0345 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05147 ,  H01L2224/05184 ,  H01L2224/05556 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/13007 ,  H01L2224/13021 ,  H01L2224/13023 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2924/00012 ,  H01L2924/13091 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01073 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/0103 ,  H01L2924/01025 ,  H01L2924/01024 ,  H01L2924/01022 ,  H01L2924/01032 ,  H01L2924/01038 ,  H01L2924/01078 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/0104 ,  H01L2924/013 ,  H01L2924/00013 ,  H01L2924/01074 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01028 ,  H01L2924/01079 ,  H01L2924/00

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a first substrate and a metal pad formed over the first substrate. The semiconductor structure further includes a seed layer formed over the metal pad and a conductive pillar formed over the seed layer. In addition, the seed layer has a sidewall and a bottom surface, and an angle between the sidewall and the bottom surface of the seed layer is in a range from about 20° to about 90°.

Abstract translation: 提供半导体结构及其形成方法。 半导体结构包括形成在第一衬底上的第一衬底和金属衬垫。 半导体结构还包括形成在金属焊盘上的种子层和形成在种子层上的导电柱。 此外，种子层具有侧壁和底表面，并且种子层的侧壁和底表面之间的角度在约20°至约90°的范围内。

公开(公告)号：US20180033756A1

公开(公告)日：2018-02-01

申请号：US15725535

申请日：2017-10-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Li-Guo LEE ,  Yi-Chen LIU ,  Yung-Sheng LIU ,  Yi-Jen LAI ,  Chun-Jen CHEN ,  Hsi-Kuei CHENG

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/81 ,  H01L2224/0345 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05147 ,  H01L2224/05184 ,  H01L2224/05556 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/13007 ,  H01L2224/13021 ,  H01L2224/13023 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2924/00012 ,  H01L2924/13091 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01073 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/0103 ,  H01L2924/01025 ,  H01L2924/01024 ,  H01L2924/01022 ,  H01L2924/01032 ,  H01L2924/01038 ,  H01L2924/01078 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/0104 ,  H01L2924/013 ,  H01L2924/00013 ,  H01L2924/01074 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01028 ,  H01L2924/01079 ,  H01L2924/00

Abstract: Methods for forming semiconductor structures are provided. The method for forming a semiconductor structure includes forming a metal pad over a first substrate and forming a polymer layer over the metal pad. The method for forming a semiconductor structure further includes forming a seed layer over the metal pad and extending over the polymer layer and forming a conductive pillar over the seed layer. The method for forming a semiconductor structure further includes wet etching the seed layer using an etchant comprising H2O2. In addition, the step of wet etching the seed layer is configured to form an extending portion having a slope sidewall.

公开(公告)号：US20150262955A1

公开(公告)日：2015-09-17

申请号：US14208948

申请日：2014-03-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Li-Guo LEE ,  Yung-Sheng LIU ,  Yi-Chen LIU ,  Yi-Jen LAI ,  Chun-Jen CHEN ,  Hsi-Kuei CHENG

IPC: H01L23/00

CPC classification number: H01L24/14 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05013 ,  H01L2224/05023 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05558 ,  H01L2224/05564 ,  H01L2224/05568 ,  H01L2224/0558 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/11462 ,  H01L2224/13006 ,  H01L2224/13007 ,  H01L2224/13014 ,  H01L2224/13023 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/1411 ,  H01L2224/16058 ,  H01L2224/16238 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/00014

Abstract: A semiconductor device structure and a manufacturing method are provided. The semiconductor device structure includes a semiconductor substrate and a dielectric layer over the semiconductor substrate. The semiconductor device structure also includes a conductive trace over the dielectric layer. The semiconductor device structure further includes a conductive feature over the conductive trace, and a width of the conductive feature is substantially equal to or larger than a maximum width of the conductive trace. In addition, the semiconductor device structure includes a conductive bump over the conductive feature.

Abstract translation: 提供半导体器件结构和制造方法。 半导体器件结构包括在半导体衬底上的半导体衬底和电介质层。 半导体器件结构还包括在电介质层上的导电迹线。 半导体器件结构还包括导电迹线上的导电特征，并且导电特征的宽度基本上等于或大于导电迹线的最大宽度。 此外，半导体器件结构包括在导电特征上的导电凸块。

公开(公告)号：US20150262954A1

公开(公告)日：2015-09-17

申请号：US14208675

申请日：2014-03-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Guo LEE ,  Yi-Chen LIU ,  Yung-Sheng LIU ,  Yi-Jen LAI ,  Chun-Jen CHEN ,  Hsi-Kuei CHENG

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/81 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05147 ,  H01L2224/05184 ,  H01L2224/05573 ,  H01L2224/0558 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/11462 ,  H01L2224/11472 ,  H01L2224/13017 ,  H01L2224/13139 ,  H01L2224/16058 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/8183 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2924/01074 ,  H01L2924/01029 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01047 ,  H01L2924/01028 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A semiconductor structure is provided. The semiconductor structure includes a first substrate and a metal pad formed over the first substrate. The semiconductor structure further includes a solder stud formed over the metal pad, and the solder stud has a flat top surface parallel to a top surface of the first substrate.

Abstract translation: 提供半导体结构。 半导体结构包括形成在第一衬底上的第一衬底和金属衬垫。 半导体结构还包括形成在金属焊盘上的焊料柱，并且焊料柱具有平行于第一衬底的顶表面的平坦顶表面。

公开(公告)号：US20150262953A1

公开(公告)日：2015-09-17

申请号：US14209118

申请日：2014-03-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Li-Guo LEE ,  Yi-Chen LIU ,  Yung-Sheng LIU ,  Yi-Jen LAI ,  Chun-Jen CHEN ,  Hsi-Kuei CHENG

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/0345 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05573 ,  H01L2224/0558 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11821 ,  H01L2224/11827 ,  H01L2224/11848 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/13006 ,  H01L2224/13007 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/13693 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2924/01074 ,  H01L2924/01029 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01082 ,  H01L2924/01079 ,  H01L2224/1182 ,  H01L2924/00012 ,  H01L2924/04953 ,  H01L2924/01047

Abstract: A semiconductor device structure and a manufacturing method are provided. The method includes forming a conductive pillar over a semiconductor substrate. The method also includes forming a solder layer over the conductive pillar. The method further includes forming a water-soluble flux over the solder layer. In addition, the method includes reflowing the solder layer to form a solder bump over the conductive pillar and form a sidewall protection layer over a sidewall of the conductive pillar during the solder layer is reflowed.

Abstract translation: 提供半导体器件结构和制造方法。 该方法包括在半导体衬底上形成导电柱。 该方法还包括在导电柱上形成焊料层。 该方法还包括在焊料层上形成水溶性助焊剂。 此外，该方法包括回流焊料层以在导电柱上形成焊料凸块，并且在焊料层回流期间在导电柱的侧壁上形成侧壁保护层。

公开(公告)号：US20150262846A1

公开(公告)日：2015-09-17

申请号：US14209023

申请日：2014-03-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Li-Guo LEE ,  Yung-Sheng LIU ,  Yi-Chen LIU ,  Yi-Jen LAI ,  Chun-Jen CHEN ,  Hsi-Kuei CHENG

IPC: H01L21/56 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L21/563 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0362 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05016 ,  H01L2224/05023 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05558 ,  H01L2224/05562 ,  H01L2224/05564 ,  H01L2224/05568 ,  H01L2224/0558 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13006 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13169 ,  H01L2224/1607 ,  H01L2224/16238 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/014

Abstract: A package structure and a manufacturing method are provided. The package structure includes a semiconductor substrate and a first conductive feature over the semiconductor substrate. The package structure also includes a substrate and a second conductive feature over the substrate. The second conductive feature is bonded with the first conductive feature through a bonding structure. The package structure further includes a protection material surrounding the bonding structure, and the protection material is in direct contact with a side surface of the first conductive feature.

Abstract translation: 提供了封装结构和制造方法。 封装结构包括半导体衬底和半导体衬底上的第一导电特征。 封装结构还包括衬底和衬底上的第二导电特征。 第二导电特征通过接合结构与第一导电特征结合。 封装结构还包括围绕接合结构的保护材料，并且保护材料与第一导电特征的侧表面直接接触。