公开(公告)号：US20240096722A1

公开(公告)日：2024-03-21

申请号：US18152539

申请日：2023-01-10

Applicant: Taiwan Semiconductor Manufacturing co., Ltd.

Inventor： Kuo-Chung Yee ,  Chia-Hui Lin ,  Shih-Peng Tai

IPC: H01L23/31 ,  H01L21/321 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L23/3128 ,  H01L21/32115 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/32245 ,  H01L2924/15311

Abstract: In an embodiment, a package includes a first device and a second device attached to a first redistribution structure, wherein the second device includes a second redistribution structure, a first die disposed over the second redistribution structure, a first encapsulant extending along sidewalls of the first die, a first via extending through the first encapsulant, a third redistribution structure disposed over the first encapsulant and including a first metallization pattern connecting to the first via, a second die disposed over the third redistribution structure, and a second encapsulant extending along sidewalls of the second die, the first die and the second die being free of through substrate vias. The package also includes a third encapsulant disposed over the first redistribution structure and surrounding sidewalls of the first device and the second device, wherein top surfaces of the second encapsulant and the third encapsulant are level with each other.

公开(公告)号：US11049945B2

公开(公告)日：2021-06-29

申请号：US16398079

申请日：2019-04-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Wen Huang ,  Yun-Wen Chu ,  Hong-Hsien Ke ,  Chia-Hui Lin ,  Shin-Yeu Tsai ,  Shih-Chieh Chang

IPC: H01L29/49 ,  H01L29/423 ,  H01L21/02 ,  H01L21/311 ,  H01L29/06 ,  H01L29/40 ,  H01L29/78 ,  H01L29/66

Abstract: Semiconductor device structures and methods for forming the same are provided. A semiconductor device structure includes a gate structure over a semiconductor substrate. The gate structure includes a gate electrode layer and a gate dielectric layer covering a bottom surface and sidewalls of the gate electrode layer. The semiconductor device structure also includes spacer elements in contact with sidewalls of the gate structure and protruding from a top surface of the gate electrode layer. The semiconductor device structure also includes a first protection layer over the gate electrode layer and between the spacer elements. The semiconductor device structure also includes a dielectric layer over the first protection layer and between the spacer elements. A portion of the dielectric layer is between sidewalls of the spacer elements and sidewalls of the first protection layer.

公开(公告)号：US20200373154A1

公开(公告)日：2020-11-26

申请号：US16983187

申请日：2020-08-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Dong-Sheng Li ,  Chia-Hui Lin ,  Kai Hung Cheng ,  Yao-Hsu Sun ,  Wen-Cheng Wu ,  Bo-Cyuan Lu ,  Sung-En Lin ,  Tai-Chun Huang

IPC: H01L21/027 ,  H01L21/02 ,  H01L21/033 ,  H01L21/28 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/8238

Abstract: A four-layer photoresist and method of forming the same are disclosed. In an embodiment, a method includes forming a semiconductor fin; depositing a target layer on the semiconductor fin; depositing a BARC layer on the target layer; depositing a first mask layer over the BARC layer, the first mask layer being deposited using a plasma process with an RF power of less than 50 W; depositing a second mask layer over the first mask layer using a plasma process with an RF power of less than 500 W; depositing a photoresist layer over the second mask layer; patterning the photoresist layer, the second mask layer, the first mask layer, and the BARC layer to form a first mask; and selectively removing the target layer from a first portion of the semiconductor fin using the first mask, the target layer remaining on a second portion of the semiconductor fin.

公开(公告)号：US20200176259A1

公开(公告)日：2020-06-04

申请号：US16680755

申请日：2019-11-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Yi Lee ,  Ting-Gang Chen ,  Chieh-Ping Wang ,  Hong-Hsien Ke ,  Chia-Hui Lin ,  Tai-Chun Huang

IPC: H01L21/28 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/3213

Abstract: A method includes etching a gate structure to form a trench extending into the gate structure, wherein sidewalls of the trench comprise a metal oxide material, applying a sidewall treatment process to the sidewalls of the trench, wherein the metal oxide material has been removed as a result of applying the sidewall treatment process and filling the trench with a first dielectric material to form a dielectric region, wherein the dielectric region is in contact with the sidewall of the gate structure.

公开(公告)号：US11296198B2

公开(公告)日：2022-04-05

申请号：US16838160

申请日：2020-04-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Wen Huang ,  Chung-Ting Ko ,  Hong-Hsien Ke ,  Chia-Hui Lin ,  Tai-Chun Huang

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/08 ,  H01L29/45 ,  H01L21/768 ,  H01L21/02 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/311 ,  H01L21/3115

Abstract: A method for forming a semiconductor structure is provided. The method includes forming a gate structure over a fin structure, forming a source/drain structure in the fin structure and adjacent to the gate structure, forming a dielectric layer over the gate structure and the source/drain structure, and forming an opening in the dielectric layer to expose the source/drain structure. The method further includes depositing a barrier layer lining a sidewall surface of the opening and a top surface of the source/drain structure. The method further includes etching a portion of the barrier layer to expose the source/drain structure. The method further includes depositing a glue layer covering the sidewall surface of the opening and the source/drain structure in the opening. The method further includes forming a contact structure filling the opening in the dielectric layer. The contact structure is surrounded by the glue layer.

公开(公告)号：US10777466B2

公开(公告)日：2020-09-15

申请号：US15922656

申请日：2018-03-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Wen Huang ,  Chia-Hui Lin ,  Jaming Chang ,  Jei Ming Chen ,  Kai Hung Cheng

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/06 ,  H01L21/02 ,  H01L21/762

Abstract: Methods of cutting fins, and structures formed thereby, are described. In an embodiment, a structure includes a first fin on a substrate, a second fin on the substrate, and a fin cut-fill structure disposed between the first fin and the second fin. The first fin and the second fin are longitudinally aligned. The fin cut-fill structure includes an insulating liner and a fill material on the insulating liner. The insulating liner abuts a first sidewall of the first fin and a second sidewall of the second fin. The insulating liner includes a material with a band gap greater than 5 eV.

公开(公告)号：US11990375B2

公开(公告)日：2024-05-21

申请号：US17852716

申请日：2022-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Wen Huang ,  Jaming Chang ,  Kai Hung Cheng ,  Chia-Hui Lin ,  Jei Ming Chen

IPC: H01L27/148 ,  H01L21/02 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06

CPC classification number: H01L21/823481 ,  H01L21/02148 ,  H01L21/02159 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02183 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/0228 ,  H01L21/76224 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0653

Abstract: Methods of cutting fins, and structures formed thereby, are described. In an embodiment, a structure includes a first fin on a substrate, a second fin on the substrate, and a fin cut-fill structure disposed between the first fin and the second fin. The first fin and the second fin are longitudinally aligned. The fin cut-fill structure includes an insulating liner and a fill material on the insulating liner. The insulating liner abuts a first sidewall of the first fin and a second sidewall of the second fin. The insulating liner includes a material with a band gap greater than 5 eV.

公开(公告)号：US20230197524A1

公开(公告)日：2023-06-22

申请号：US18168383

申请日：2023-02-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Yi Lee ,  Hong-Hsien Ke ,  Chung-Ting Ko ,  Chia-Hui Lin ,  Jr-Hung Li

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/311 ,  C23C16/34 ,  C23C16/455

CPC classification number: H01L21/823468 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/02211 ,  H01L21/31116 ,  H01L21/823431 ,  C23C16/345 ,  C23C16/45542 ,  H01L21/0217 ,  H01L21/0228

Abstract: An etch stop layer is formed over a semiconductor fin and gate stack. The etch stop layer is formed utilizing a series of pulses of precursor materials. A first pulse introduces a first precursor material to the semiconductor fin and gate stack. A second pulse introduces a second precursor material, which is turned into a plasma and then directed towards the semiconductor fin and gate stack in an anisotropic deposition process. As such, a thickness of the etch stop layer along a bottom surface is larger than a thickness of the etch stop layer along sidewalls.

公开(公告)号：US09324603B2

公开(公告)日：2016-04-26

申请号：US13967558

申请日：2013-08-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Yeu Tsai ,  Chia-Hui Lin ,  Ching-Yu Chen ,  Chui-Ya Peng

IPC: H01L21/762

CPC classification number: H01L21/76224 ,  H01L21/76229

Abstract: A method is disclosed that includes the operations outlined below. An insulating material is disposed within a plurality of trenches on a semiconductor substrate and over the semiconductor substrate. The first layer is formed over the insulating material. The first layer and the insulating material are removed.

Abstract translation: 公开了一种包括以下概述的操作的方法。 绝缘材料设置在半导体衬底上并在半导体衬底之上的多个沟槽内。 第一层形成在绝缘材料上。 去除第一层和绝缘材料。

公开(公告)号：US20250087528A1

公开(公告)日：2025-03-13

申请号：US18402187

申请日：2024-01-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yunn-Shiuan Liu ,  Li-Fong Lin ,  Chia-Hui Lin ,  Tze-Liang Lee

IPC: H01L21/762 ,  H01L27/088 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A method includes forming a gate stack, and etching the gate stack to form a trench penetrating through the gate stack. A dielectric isolation region underlying the gate stack is exposed to the trench, and a first portion and a second portion of the gate stack are separated by the trench. The method includes performing a first deposition process to form a first dielectric layer extending into the trench and lining sidewalls of the first portion and the second portion of the gate stack, and performing a second deposition process to form a second dielectric layer on the first dielectric layer. The second dielectric layer fills the trench. The first dielectric layer has a first dielectric constant, and the second dielectric layer has a second dielectric constant greater than the first dielectric constant.