公开(公告)号：US20210327528A1

公开(公告)日：2021-10-21

申请号：US16851107

申请日：2020-04-17

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Mao-Ruei Li ,  Fan-Ming Kuo ,  Wei-Li Chen

IPC分类号： G11C29/42 ,  G11C29/44 ,  G11C29/46 ,  G11C29/12 ,  G11C29/56

摘要： A data verifying method, a chip, and a verifying apparatus are provided. In the method, an encoder is provided for at least one processing circuit of a chip. One or more transmitting data of a to-be-test circuit of the processing circuit is encoded through the encoder to generate one or more parity data. The transmitting data is a computing result generated by the to-be-test circuit. The parity data is transmitted without the transmitting data. The parity data is used for data verification of the transmitting data.

公开(公告)号：US11183262B2

公开(公告)日：2021-11-23

申请号：US16851107

申请日：2020-04-17

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Mao-Ruei Li ,  Fan-Ming Kuo ,  Wei-Li Chen

IPC分类号： G11C29/00 ,  G11C29/42 ,  G11C29/44 ,  G11C29/12 ,  G11C29/56 ,  G11C29/46

摘要： A data verifying method, a chip, and a verifying apparatus are provided. In the method, an encoder is provided for at least one processing circuit of a chip. One or more transmitting data of a to-be-test circuit of the processing circuit is encoded through the encoder to generate one or more parity data. The transmitting data is a computing result generated by the to-be-test circuit. The parity data is transmitted without the transmitting data. The parity data is used for data verification of the transmitting data.

公开(公告)号：US10855291B1

公开(公告)日：2020-12-01

申请号：US16835254

申请日：2020-03-30

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yu-Tso Lin ,  Chin-Ming Fu ,  Mao-Ruei Li

IPC分类号： H03L7/085 ,  H03L7/081

摘要： The disclosure provides a delay estimation device and a delay estimation method. The delay estimation device includes a pulse generator, a digitally controlled delay line (DCDL), a time-to-digital converter (TDC), and a control circuit. The pulse generator receives a reference clock signal, outputs a first clock signal in response to a first rising edge of the reference clock signal, and outputs a second clock signal in response to a second rising edge of the reference clock signal. The DCDL receives the first clock signal from the pulse generator and converts the first clock signal into phase signals based on a combination of delay line codes. The TDC samples the phase signals to generate a timing code based on the second clock signal. The control circuit estimates a specific delay between the first clock signal and the second clock signal based on the timing code.