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公开(公告)号：US11183262B2
公开(公告)日：2021-11-23
申请号：US16851107
申请日：2020-04-17
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Mao-Ruei Li , Fan-Ming Kuo , Wei-Li Chen
Abstract: A data verifying method, a chip, and a verifying apparatus are provided. In the method, an encoder is provided for at least one processing circuit of a chip. One or more transmitting data of a to-be-test circuit of the processing circuit is encoded through the encoder to generate one or more parity data. The transmitting data is a computing result generated by the to-be-test circuit. The parity data is transmitted without the transmitting data. The parity data is used for data verification of the transmitting data.
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2.发明申请公开(公告)号：US20140184296A1
公开(公告)日：2014-07-03
申请号：US13727850
申请日：2012-12-27
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Tsung-Hsiung Lee , Shi-Hung Wang , Kuang-Kai Yen , Wei-Li Chen , Yung-Hsu Chuang , Shih-Hung Lan , Fan-Ming Kuo , Chewn-Pu Jou , Fu-Lung Hsueh
IPC: H03K3/012 , H03K3/3562 , H03K3/037
CPC classification number: H03K3/012 , H03K3/356008 , H03K3/356043 , H03K3/3562
Abstract: The present disclosure relates to a device and method to reduce the dynamic/static power consumption of an MCML logic device. In order to retain register contents during power off mode, an MCML retention latch and flip-flop are disclosed. Retention Latch circuits in MCML architecture are used to retain critical register contents during power off mode, wherein combination logic including clock buffers on the clock tree paths are powered off to reduce dynamic/static power consumption. The MCML retention flip-flop comprises a master latch and a slave latch, wherein a power switch is added to the master latch to power the master latch off during power off mode. The slave latch includes pull-down circuits that remain active to enable the slave latch to retain data at a proper voltage level during power off mode. Other devices and methods are also disclosed.
Abstract translation: 本公开涉及一种减少MCML逻辑器件的动态/静态功耗的装置和方法。 为了在断电模式下保持寄存器内容，公开了一种MCML保持锁存器和触发器。 保留MCML架构中的锁存电路用于在断电模式下保留关键寄存器内容，其中包括时钟树路径上的时钟缓冲器的组合逻辑被关闭以减少动态/静态功耗。 MCML保持触发器包括主锁存器和从锁存器，其中在断电模式期间将电源开关加到主锁存器以为主锁存器供电。 从锁存器包括保持有效的下拉电路，以使从锁存器在断电模式期间将数据保持在适当的电压电平。 还公开了其它装置和方法。
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公开(公告)号：US20210327528A1
公开(公告)日：2021-10-21
申请号：US16851107
申请日：2020-04-17
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Mao-Ruei Li , Fan-Ming Kuo , Wei-Li Chen
Abstract: A data verifying method, a chip, and a verifying apparatus are provided. In the method, an encoder is provided for at least one processing circuit of a chip. One or more transmitting data of a to-be-test circuit of the processing circuit is encoded through the encoder to generate one or more parity data. The transmitting data is a computing result generated by the to-be-test circuit. The parity data is transmitted without the transmitting data. The parity data is used for data verification of the transmitting data.
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公开(公告)号：US09991721B2
公开(公告)日：2018-06-05
申请号：US14918615
申请日：2015-10-21
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Jun-De Jin , Fan-Ming Kuo , Huan-Neng Chen , Ming-Hsien Tsai , Hsieh-Hung Hsieh , Tzu-Jin Yeh
CPC classification number: H02J5/005 , H01F5/00 , H01F17/0006 , H01F38/14 , H01F2017/0086 , H02J17/00 , H02J50/12
Abstract: A transformer includes first and second semiconductor substrates. The first semiconductor substrate includes a first circuit, a first coil providing a first impedance, and a first capacitor coupled in parallel with the first coil. The second semiconductor substrate includes a second circuit, a second coil providing a second impedance and inductively coupled with the first coil, and a second capacitor coupled in parallel with the second coil.
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