公开(公告)号：US20220013580A1

公开(公告)日：2022-01-13

申请号：US16924162

申请日：2020-07-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mauricio MANFRINI ,  Chung-Te Lin ,  Ken-Ichi Goto

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12 ,  H01L43/10 ,  H01L29/423 ,  H01L23/528

Abstract: A semiconductor device includes a semiconductor substrate and an interconnection region disposed on the semiconductor substrate. The interconnection region includes stacked metallization levels, a magnetic tunnel junction, and a transistor. The magnetic tunnel junction is formed on a first conductive pattern of a first metallization level of the stacked metallization levels. The transistor is formed on a second conductive pattern of a second metallization level of the stacked metallization levels. The transistor is a vertical gate-all-around transistor. A drain contact of the transistor is electrically connected to the magnetic tunnel junction by the first conductive pattern of the first metallization level. The second metallization level is closer to the semiconductor substrate than the first metallization level.

公开(公告)号：US20220020919A1

公开(公告)日：2022-01-20

申请号：US16933914

申请日：2020-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Georgios Vellianitis ,  Gerben Doornbos ,  Marcus Johannes Henricus Van Dal ,  Mauricio MANFRINI

IPC: H01L43/04 ,  H01L43/06 ,  H01L27/22 ,  H01L43/10 ,  H01L43/14

Abstract: A semiconductor device includes a storage element layer and a selector. The selector is electrically coupled to the storage element layer, and includes a first insulating layer, a second insulating layer, a third insulating layer, a first conductive layer and a second conductive layer. The first insulating layer, the second insulating layer and the third insulating layer are stacked up in sequence, wherein the second insulating layer is sandwiched in between the first insulating layer and the third insulating layer, and the first insulating layer and the third insulating layer include materials with higher band gap as compared with a material of the second insulating layer. The first conductive layer is connected to the first insulting layer, and the second conductive layer is connected to the third insulating layer.

公开(公告)号：US20220013712A1

公开(公告)日：2022-01-13

申请号：US16924214

申请日：2020-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mauricio MANFRINI

IPC: H01L43/02 ,  H01L43/12 ,  H01L27/22

Abstract: A back-end-of-line transistor includes a channel strip, a source contact, a drain contact, a high-k dielectric strip, a gate pattern, and self-assembled monolayers. The channel strip includes a semiconductor oxide material. The source contact contacts a first end of the channel strip. The drain contact contacts a second end of the channel strip. The high-k dielectric strip extends on the channel strip in between the first end and the second end of the channel strip. The gate pattern extends on the high-k dielectric strip. The self-assembled monolayers are disposed in between the channel strip and the source and drain contacts. The self-assembled monolayers include a compound having a polar group. The polar group is bonded to at least one selected from the channel strip, the source contact, and the drain contact.