公开(公告)号：US11024801B2

公开(公告)日：2021-06-01

申请号：US16210226

申请日：2018-12-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jung-Tang Wu ,  Jui-Hung Ho ,  Chin-Szu Lee ,  Meng-Yu Wu ,  Szu-Hua Wu

IPC: H01L45/00 ,  H01L43/02 ,  H01L21/768 ,  H01L43/12 ,  H01L23/532

Abstract: The present disclosure describes an exemplary method that can prevent or reduce out-diffusion of Cu from interconnect layers to magnetic tunnel junction (MTJ) structures. The method includes forming an interconnect layer over a substrate that includes an interlayer dielectric stack with openings therein; disposing a metal in the openings to form corresponding conductive structures; and selectively depositing a diffusion barrier layer on the metal. In the method, selectively depositing the diffusion barrier layer includes pre-treating the surface of the metal; disposing a precursor to selectively form a partially-decomposed precursor layer on the metal; and exposing the partially-decomposed precursor layer to a plasma to form the diffusion barrier layer. The method further includes forming an MTJ structure on the interconnect layer over the diffusion barrier layer, where the bottom electrode of the MTJ structure is aligned to the diffusion barrier layer.

公开(公告)号：US11515474B2

公开(公告)日：2022-11-29

申请号：US17112861

申请日：2020-12-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jung-Tang Wu ,  Szu-Ping Tung ,  Szu-Hua Wu ,  Shing-Chyang Pan ,  Meng-Yu Wu

IPC: H01L43/12 ,  H01L43/02 ,  H01L27/22

Abstract: A memory device includes a semiconductor substrate, a first dielectric layer, a metal contact, an aluminum nitride layer, an aluminum oxide layer, a second dielectric layer, a metal via, and a memory stack. The first dielectric layer is over the semiconductor substrate. The metal contact passes through the first dielectric layer. The aluminum nitride layer extends along a top surface of the first dielectric layer and a top surface of the metal contact. The aluminum oxide layer extends along a top surface of the aluminum nitride layer. The second dielectric layer is over the aluminum oxide layer. The metal via passes through the second dielectric layer, the aluminum oxide layer, and the aluminum nitride layer and lands on the metal contact. The memory stack lands on the metal via.

公开(公告)号：US10535816B2

公开(公告)日：2020-01-14

申请号：US16059777

申请日：2018-08-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jung-Tang Wu ,  Szu-Ping Tung ,  Szu-Hua Wu ,  Shing-Chyang Pan ,  Meng-Yu Wu

IPC: H01L43/12 ,  H01L27/22 ,  H01L43/02

Abstract: A via structure, a MRAM device using the via structure and a method for fabricating the MRAM device are provided. In the method for fabricating the MRAM device, at first, a first dielectric layer is deposited over a transistor. Then, a contact is formed in the first dielectric layer and electrically connected to the transistor. Thereafter, a metal nitride layer is deposited over the first dielectric layer and the contact. Then, an etch stop layer is deposited over the metal nitride layer. Thereafter, a second dielectric layer is deposited over the etch stop layer. Then, a via structure is formed in the second dielectric layer, the etch stop layer, and the metal nitride layer and landing on the contact. Thereafter, a memory stack is formed over the via structure.

公开(公告)号：US11985904B2

公开(公告)日：2024-05-14

申请号：US17168974

申请日：2021-02-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Jen Chien ,  Jung-Tang Wu ,  Szu-Hua Wu ,  Chin-Szu Lee ,  Meng-Yu Wu

IPC: H10N50/01 ,  H10B61/00 ,  H10N50/80

CPC classification number: H10N50/01 ,  H10B61/22 ,  H10N50/80

Abstract: A method of manufacturing a semiconductor device includes: providing a substrate, the substrate defining a logic region and a memory region; depositing a bottom electrode layer across the logic region and the memory region; depositing a magnetic tunnel junction (MTJ) layer over the bottom electrode layer; depositing a first conductive layer over the MTJ layer; depositing a sacrificial layer over the first conductive layer; etching the sacrificial layer in the memory region to expose the first conductive layer in the memory region while keeping the first conductive layer in the logic region covered; depositing a second conductive layer in the memory region and the logic region; patterning the second conductive layer to expose the MTJ layer in the memory region; and etching the patterned second conductive layer and the MTJ layer to form a top electrode and an MTJ, respectively, in the memory region.

公开(公告)号：US20230137291A1

公开(公告)日：2023-05-04

申请号：US18148829

申请日：2022-12-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jung-Tang WU ,  Jui-Hung Ho ,  Chin-Szu Lee ,  Meng-Yu Wu ,  Szu-Hua Wu

IPC: H10N50/01 ,  H10N50/80 ,  H01L21/768 ,  H01L23/532 ,  H10N70/00

Abstract: The present disclosure describes an exemplary method that can prevent or reduce out-diffusion of Cu from interconnect layers to magnetic tunnel junction (MTJ) structures. The method includes forming an interconnect layer over a substrate that includes an interlayer dielectric stack with openings therein; disposing a metal in the openings to form corresponding conductive structures; and selectively depositing a diffusion barrier layer on the metal. In the method, selectively depositing the diffusion barrier layer includes pre-treating the surface of the metal; disposing a precursor to selectively form a partially-decomposed precursor layer on the metal; and exposing the partially-decomposed precursor layer to a plasma to form the diffusion barrier layer. The method further includes forming an MTJ structure on the interconnect layer over the diffusion barrier layer, where the bottom electrode of the MTJ structure is aligned to the diffusion barrier layer.

公开(公告)号：US11991930B2

公开(公告)日：2024-05-21

申请号：US17984066

申请日：2022-11-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO, LTD.

Inventor： Jung-Tang Wu ,  Szu-Ping Tung ,  Szu-Hua Wu ,  Shing-Chyang Pan ,  Meng-Yu Wu

IPC: H01L43/12 ,  H01L27/22 ,  H01L43/02 ,  H10B61/00 ,  H10N50/01 ,  H10N50/80

CPC classification number: H10N50/01 ,  H10B61/22 ,  H10N50/80

Abstract: A structure includes a substrate, a transistor, a contact, an oxygen-free etch stop layer, an oxygen-containing etch stop layer, a dielectric layer, and a via. The transistor is on the substrate. The contact is on a source/drain region of the transistor. The oxygen-free etch stop layer spans the contact. The oxygen-containing etch stop layer extends along a top surface of the oxygen-free etch stop layer. The dielectric layer is over the oxygen-containing etch stop layer. The via passes through the dielectric layer, the oxygen-containing etch stop layer, and the oxygen-free etch stop layer and lands on the contact. The memory stack lands on the via.

公开(公告)号：US10862026B2

公开(公告)日：2020-12-08

申请号：US16741557

申请日：2020-01-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jung-Tang Wu ,  Szu-Ping Tung ,  Szu-Hua Wu ,  Shing-Chyang Pan ,  Meng-Yu Wu

IPC: H01L43/12 ,  H01L27/22 ,  H01L43/02

Abstract: A memory device includes a semiconductor substrate, a first dielectric layer, a metal contact, a metal nitride layer, an etch stop layer, a second dielectric layer, a metal via, and a memory stack. The first dielectric layer is over the semiconductor substrate. The metal contact passes through the first dielectric layer. The metal nitride layer spans the first dielectric layer and the metal contact. The etch stop layer extends along a top surface of the metal nitride layer, in which a thickness of the metal nitride layer is less than a thickness of the etch stop layer. The second dielectric layer is over the etch stop layer. The metal via passes through the second dielectric layer, the etch stop layer, and the metal nitride layer and lands on the metal contact. The memory stack is in contact with the metal via.

公开(公告)号：US11696510B2

公开(公告)日：2023-07-04

申请号：US17334536

申请日：2021-05-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jung-Tang Wu ,  Jui-Hung Ho ,  Chin-Szu Lee ,  Meng-Yu Wu ,  Szu-Hua Wu

IPC: H01L21/12 ,  H10N50/01 ,  H01L21/768 ,  H01L23/532 ,  H10N50/80 ,  H10N70/00

CPC classification number: H10N50/01 ,  H01L21/7685 ,  H01L21/76802 ,  H01L21/76841 ,  H01L21/76849 ,  H01L23/53238 ,  H10N50/80 ,  H10N70/826

Abstract: The present disclosure describes an exemplary method that can prevent or reduce out-diffusion of Cu from interconnect layers to magnetic tunnel junction (MTJ) structures. The method includes forming an interconnect layer over a substrate that includes an interlayer dielectric stack with openings therein; disposing a metal in the openings to form corresponding conductive structures; and selectively depositing a diffusion barrier layer on the metal. In the method, selectively depositing the diffusion barrier layer includes pre-treating the surface of the metal; disposing a precursor to selectively form a partially-decomposed precursor layer on the metal; and exposing the partially-decomposed precursor layer to a plasma to form the diffusion barrier layer. The method further includes forming an MTJ structure on the interconnect layer over the diffusion barrier layer, where the bottom electrode of the MTJ structure is aligned to the diffusion barrier layer.