公开(公告)号：US11696510B2

公开(公告)日：2023-07-04

申请号：US17334536

申请日：2021-05-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jung-Tang Wu ,  Jui-Hung Ho ,  Chin-Szu Lee ,  Meng-Yu Wu ,  Szu-Hua Wu

IPC: H01L21/12 ,  H10N50/01 ,  H01L21/768 ,  H01L23/532 ,  H10N50/80 ,  H10N70/00

CPC classification number: H10N50/01 ,  H01L21/7685 ,  H01L21/76802 ,  H01L21/76841 ,  H01L21/76849 ,  H01L23/53238 ,  H10N50/80 ,  H10N70/826

Abstract: The present disclosure describes an exemplary method that can prevent or reduce out-diffusion of Cu from interconnect layers to magnetic tunnel junction (MTJ) structures. The method includes forming an interconnect layer over a substrate that includes an interlayer dielectric stack with openings therein; disposing a metal in the openings to form corresponding conductive structures; and selectively depositing a diffusion barrier layer on the metal. In the method, selectively depositing the diffusion barrier layer includes pre-treating the surface of the metal; disposing a precursor to selectively form a partially-decomposed precursor layer on the metal; and exposing the partially-decomposed precursor layer to a plasma to form the diffusion barrier layer. The method further includes forming an MTJ structure on the interconnect layer over the diffusion barrier layer, where the bottom electrode of the MTJ structure is aligned to the diffusion barrier layer.

公开(公告)号：US20240387155A1

公开(公告)日：2024-11-21

申请号：US18786523

申请日：2024-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jung-Tang Wu ,  Szu-Hua Wu ,  Chin-Szu Lee ,  Yi-Lin Wang

IPC: H01J37/34 ,  C23C14/16 ,  C23C14/34 ,  H01J37/32 ,  H01L21/285 ,  H10N50/01

Abstract: A method includes placing a wafer on a wafer holder, depositing a film on a front surface of the wafer, and blowing a gas through ports in a redistributor onto a back surface of the wafer at a same time the deposition is performed. The gas is selected from a group consisting of nitrogen (N2), He, Ne, and combinations thereof.

公开(公告)号：US20210296571A1

公开(公告)日：2021-09-23

申请号：US17339785

申请日：2021-06-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jung-Tang Wu ,  Yu-Jen Chien ,  Szu-Hua Wu ,  Chin-Szu Lee ,  Yao-Shien Huang

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12

Abstract: A method of forming a semiconductor structure includes forming a first top electrode (TE) layer over a magnetic tunnel junction (MTJ) layer and performing a smoothing treatment on the first TE layer. The smoothing treatment is performed in situ after the forming first TE layer. The smoothing treatment removes spike point defects from the first TE layer. Additional TE layers may be formed over the first TE layer.

公开(公告)号：US11024801B2

公开(公告)日：2021-06-01

申请号：US16210226

申请日：2018-12-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jung-Tang Wu ,  Jui-Hung Ho ,  Chin-Szu Lee ,  Meng-Yu Wu ,  Szu-Hua Wu

IPC: H01L45/00 ,  H01L43/02 ,  H01L21/768 ,  H01L43/12 ,  H01L23/532

Abstract: The present disclosure describes an exemplary method that can prevent or reduce out-diffusion of Cu from interconnect layers to magnetic tunnel junction (MTJ) structures. The method includes forming an interconnect layer over a substrate that includes an interlayer dielectric stack with openings therein; disposing a metal in the openings to form corresponding conductive structures; and selectively depositing a diffusion barrier layer on the metal. In the method, selectively depositing the diffusion barrier layer includes pre-treating the surface of the metal; disposing a precursor to selectively form a partially-decomposed precursor layer on the metal; and exposing the partially-decomposed precursor layer to a plasma to form the diffusion barrier layer. The method further includes forming an MTJ structure on the interconnect layer over the diffusion barrier layer, where the bottom electrode of the MTJ structure is aligned to the diffusion barrier layer.

公开(公告)号：US11991930B2

公开(公告)日：2024-05-21

申请号：US17984066

申请日：2022-11-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO, LTD.

Inventor： Jung-Tang Wu ,  Szu-Ping Tung ,  Szu-Hua Wu ,  Shing-Chyang Pan ,  Meng-Yu Wu

IPC: H01L43/12 ,  H01L27/22 ,  H01L43/02 ,  H10B61/00 ,  H10N50/01 ,  H10N50/80

CPC classification number: H10N50/01 ,  H10B61/22 ,  H10N50/80

Abstract: A structure includes a substrate, a transistor, a contact, an oxygen-free etch stop layer, an oxygen-containing etch stop layer, a dielectric layer, and a via. The transistor is on the substrate. The contact is on a source/drain region of the transistor. The oxygen-free etch stop layer spans the contact. The oxygen-containing etch stop layer extends along a top surface of the oxygen-free etch stop layer. The dielectric layer is over the oxygen-containing etch stop layer. The via passes through the dielectric layer, the oxygen-containing etch stop layer, and the oxygen-free etch stop layer and lands on the contact. The memory stack lands on the via.

公开(公告)号：US20230389438A1

公开(公告)日：2023-11-30

申请号：US18447383

申请日：2023-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jung-Tang Wu ,  Wu Meng Yu ,  Szu-Hua Wu ,  Chin-Szu Lee ,  Han-Ting Tsai ,  Yu-Jen Chien

IPC: H10N50/01 ,  H01F10/32 ,  H10B61/00 ,  G11C11/16 ,  H01F41/34 ,  H10N50/80

CPC classification number: H10N50/01 ,  H01F10/3254 ,  H10B61/00 ,  G11C11/161 ,  H01F41/34 ,  H10N50/80

Abstract: A top electrode of a magnetoresistive random access memory (MRAM) device over a magnetic tunnel junction (MTJ) is formed using a film of titanium nitride oriented in a (111) crystal structure rather than a top electrode which uses tantalum, tantalum nitride, and/or a multilayer including tantalum and tantalum nitride.

公开(公告)号：US11749524B2

公开(公告)日：2023-09-05

申请号：US17339785

申请日：2021-06-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jung-Tang Wu ,  Yu-Jen Chien ,  Szu-Hua Wu ,  Chin-Szu Lee ,  Yao-Shien Huang

IPC: H01L21/02 ,  H01L21/28 ,  H01L21/04 ,  H10B61/00 ,  H10N50/01

CPC classification number: H01L21/0234 ,  H01L21/044 ,  H01L21/28088 ,  H10B61/00 ,  H10N50/01

Abstract: A method of forming a semiconductor structure includes forming a first top electrode (TE) layer over a magnetic tunnel junction (MTJ) layer and performing a smoothing treatment on the first TE layer. The smoothing treatment is performed in situ after the forming first TE layer. The smoothing treatment removes spike point defects from the first TE layer. Additional TE layers may be formed over the first TE layer.

公开(公告)号：US10862026B2

公开(公告)日：2020-12-08

申请号：US16741557

申请日：2020-01-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jung-Tang Wu ,  Szu-Ping Tung ,  Szu-Hua Wu ,  Shing-Chyang Pan ,  Meng-Yu Wu

IPC: H01L43/12 ,  H01L27/22 ,  H01L43/02

Abstract: A memory device includes a semiconductor substrate, a first dielectric layer, a metal contact, a metal nitride layer, an etch stop layer, a second dielectric layer, a metal via, and a memory stack. The first dielectric layer is over the semiconductor substrate. The metal contact passes through the first dielectric layer. The metal nitride layer spans the first dielectric layer and the metal contact. The etch stop layer extends along a top surface of the metal nitride layer, in which a thickness of the metal nitride layer is less than a thickness of the etch stop layer. The second dielectric layer is over the etch stop layer. The metal via passes through the second dielectric layer, the etch stop layer, and the metal nitride layer and lands on the metal contact. The memory stack is in contact with the metal via.

公开(公告)号：US11864467B2

公开(公告)日：2024-01-02

申请号：US17461132

申请日：2021-08-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jung-Tang Wu ,  Wu Meng Yu ,  Szu-Hua Wu ,  Chin-Szu Lee ,  Han-Ting Tsai ,  Yu-Jen Chien

IPC: H10N50/01 ,  H01F41/34 ,  G11C11/16 ,  H01F10/32 ,  H10B61/00 ,  H10N50/80

CPC classification number: H10N50/01 ,  G11C11/161 ,  H01F10/3254 ,  H01F41/34 ,  H10B61/00 ,  H10N50/80

Abstract: A top electrode of a magnetoresistive random access memory (MRAM) device over a magnetic tunnel junction (MTJ) is formed using a film of titanium nitride oriented in a (111) crystal structure rather than a top electrode which uses tantalum, tantalum nitride, and/or a multilayer including tantalum and tantalum nitride.

公开(公告)号：US11791206B2

公开(公告)日：2023-10-17

申请号：US16940247

申请日：2020-07-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jung-Tang Wu ,  Pao-Sheng Chen ,  Pei-Hsuan Lee ,  Szu-Hua Wu ,  Chih-Chien Chi

IPC: H01L21/768 ,  H01L21/67 ,  H01L21/02

CPC classification number: H01L21/76877 ,  H01L21/02063 ,  H01L21/02068 ,  H01L21/67028

Abstract: A method for forming a semiconductor device, includes: forming a metal layer on a semiconductor substrate; forming a dielectric layer over the metal layer; etching a top portion of the dielectric layer; after etching the top portion of the dielectric layer, removing first mist from a bottom portion of the dielectric layer; removing the bottom portion of the dielectric layer to expose the metal layer; performing a pre-clean operation, using an alcohol base vapor or an aldehyde base vapor, on the dielectric layer and the metal layer; and forming a conductor extending through the dielectric layer and in contact with the metal layer.