公开(公告)号：US20170162395A1

公开(公告)日：2017-06-08

申请号：US15435168

申请日：2017-02-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Ta WU ,  Shiu-Ko JANGJIAN ,  Chung-Ren SUN ,  Ming-Te CHEN ,  Ting-Chun WANG ,  Jun-Jie CHENG

IPC: H01L21/28 ,  H01L21/762 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/66795 ,  H01L21/76224 ,  H01L29/7851

Abstract: A semiconductor device includes a semiconductor fin, a lining oxide layer, a silicon nitride based layer and a gate oxide layer. The semiconductor fin has a top fin surface, an upper fin side surface portion adjacent to the top fin surface, and a lower fin side surface contiguously connected to the upper fin side surface portion. The lining oxide layer peripherally encloses the lower fin side surface portion of the semiconductor fin. The silicon nitride based layer is disposed conformally over the lining oxide layer. The gate oxide layer is disposed conformally over the top fin surface and the upper fin side surface portion.

公开(公告)号：US20240234530A1

公开(公告)日：2024-07-11

申请号：US18330229

申请日：2023-06-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hsiung TSAI ,  Yu-Ming LIN ,  Kuo-Feng YU ,  Yu-Ting LIN ,  Ming-Te CHEN ,  Yi-Hsiu HUANG

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/775 ,  H01L29/78696

Abstract: A device includes: a stack of nanostructure channels over a substrate; a gate structure wrapping around the stack; and a source/drain region on the substrate. The source/drain region includes: a first epitaxial layer in direct contact with the channels; and a second epitaxial layer on the first epitaxial layer, the second epitaxial layer having higher germanium concentration than the first epitaxial layer. The device further includes a bottom isolation structure between the source/drain region and the substrate, the bottom isolation structure being a dielectric layer that is in direct contact with the source/drain region.

公开(公告)号：US20210082707A1

公开(公告)日：2021-03-18

申请号：US16573596

申请日：2019-09-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Miao-Syuan FAN ,  Ching-Hua LEE ,  Ming-Te CHEN ,  Jung-Wei LEE ,  Pei-Wei LEE

IPC: H01L21/285 ,  H01L21/02 ,  H01L29/66

Abstract: A semiconductor device includes a gate structure disposed over a channel region, a source/drain epitaxial layer disposed at a source/drain region, a nitrogen containing layer disposed on the source/drain epitaxial layer, a silicide layer disposed on the nitrogen containing layer, and a conductive contact disposed on the silicide layer.

公开(公告)号：US20170032970A1

公开(公告)日：2017-02-02

申请号：US14814370

申请日：2015-07-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Ta WU ,  Shiu-Ko JANGJIAN ,  Chung-Ren SUN ,  Ming-Te CHEN ,  Ting-Chun WANG ,  Jun-Jie CHENG

IPC: H01L21/28 ,  H01L29/78 ,  H01L29/06 ,  H01L21/762 ,  H01L29/66

CPC classification number: H01L29/66795 ,  H01L21/76224 ,  H01L29/7851

Abstract: A semiconductor device includes a semiconductor fin, a lining oxide layer, a silicon nitride based layer and a gate oxide layer. The semiconductor fin has a top surface, a first side surface adjacent to the top surface, and a second side surface which is disposed under and adjacent to the first side surface. The lining oxide layer peripherally encloses the second side surface of the semiconductor fin. The silicon nitride based layer is disposed conformal to the lining oxide layer. The gate oxide layer is disposed conformal to the top surface and the first side surface.

Abstract translation: 半导体器件包括半导体鳍片，衬里氧化物层，氮化硅基层和栅极氧化物层。 半导体翅片具有顶表面，与顶表面相邻的第一侧表面，以及设置在第一侧表面下方并与其邻近的第二侧表面。 衬里氧化物层周边地包围半导体鳍片的第二侧表面。 氮化硅基层与衬里氧化物层一致地设置。 栅极氧化物层与顶表面和第一侧表面共形设置。

公开(公告)号：US20150187616A1

公开(公告)日：2015-07-02

申请号：US14144657

申请日：2013-12-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Chun HUANG ,  Lee-Te TSENG ,  Wen-Chieh HUANG ,  Chi-Fu YU ,  Ming-Te CHEN

IPC: H01L21/67 ,  H01L21/324 ,  H01L21/268

CPC classification number: H01L21/67115 ,  B23K26/0665 ,  B23K26/0732 ,  B23K26/083 ,  B23K26/0892 ,  H01L21/268 ,  H01L21/324

Abstract: Mechanisms of adjustable laser beams for LSA (Laser Spike Annealing) are provided. A computing device receives input mask information relative to a silicon wafer, and analyzes the input mask information so as to generate a control signal. A laser generator generates a laser beam, and adjusts a beam length of the laser beam according to the control signal. Such mechanisms of the disclosure effectively eliminate the stitch effect on the silicon wafer and further increase the wafer yield.

Abstract translation: 提供LSA（激光尖峰退火）可调激光束的机理。 计算装置接收相对于硅晶片的输入掩模信息，并且分析输入掩模信息以产生控制信号。 激光发生器产生激光束，并根据控制信号调整激光束的光束长度。 本公开的这种机构有效地消除了对硅晶片的针脚效应，并进一步提高了晶片的产量。

公开(公告)号：US20210074593A1

公开(公告)日：2021-03-11

申请号：US16562395

申请日：2019-09-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chandrashekhar Prakash SAVANT ,  Chia-Ming TSAI ,  Ming-Te CHEN ,  Tien-Wei YU

IPC: H01L21/8238 ,  H01L27/092

Abstract: A semiconductor device includes a gate structure disposed over a channel region, and a source/drain region. The gate structure includes a gate dielectric layer over the channel region, a first work function adjustment layer, over the gate dielectric layer, a first shield layer over the first work function adjustment layer, a first barrier layer, and a metal gate electrode layer. The first work function adjustment layer is made up of n-type work function adjustment layer and includes aluminum. The first shield layer is made of at least one selected from the group consisting of metal, metal nitride, metal carbide, silicide, a layer containing one or more of F, Ga, In, Zr, Mn and Sn, and an aluminum containing layer having a lower aluminum concentration than the first work function adjustment layer.

公开(公告)号：US20150221515A1

公开(公告)日：2015-08-06

申请号：US14170837

申请日：2014-02-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Kuo-Yuan HO ,  Jung-Wei LEE ,  Ming-Te CHEN

IPC: H01L21/265 ,  H01L21/67 ,  H01L21/324

CPC classification number: H01L21/26593 ,  H01L21/67109 ,  H01L21/67115 ,  H01L21/67201 ,  H01L21/67213 ,  H01L21/67745

Abstract: Embodiments of method for cooling a wafer in an ion implantation process are provided. A method for cooling the wafer in the ion implantation process includes placing the wafer in a process module. The method also includes performing the ion implantation process on the wafer and simultaneously cooling the wafer in the process module. The method further includes removing the wafer from the process module. In addition, the method includes heating up the wafer.

Abstract translation: 提供了在离子注入工艺中冷却晶片的方法的实施例。 用于在离子注入工艺中冷却晶片的方法包括将晶片放置在处理模块中。 该方法还包括在晶片上执行离子注入工艺并同时冷却处理模块中的晶片。 该方法还包括从处理模块移除晶片。 此外，该方法包括加热晶片。