公开(公告)号：US20190165100A1

公开(公告)日：2019-05-30

申请号：US15922643

申请日：2018-03-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-I KUO ,  Chii-Horng LI ,  Chia-Ling CHAN ,  Li-Li SU ,  Yi-Fang PAI ,  Wei Te CHIANG ,  Shao-Fu FU ,  Wei Hao LU

IPC: H01L29/08 ,  H01L29/167 ,  H01L29/36 ,  H01L21/223 ,  H01L21/02 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0847 ,  H01L21/02521 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/0262 ,  H01L21/2236 ,  H01L21/30604 ,  H01L21/3065 ,  H01L29/167 ,  H01L29/36 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7851

Abstract: The present disclosure relates generally to an epitaxy scheme for forming source/drain regions in a semiconductor device, such as an n-channel device. In an example, a method of manufacturing a semiconductor device includes forming an active area on a substrate. The active area includes a source/drain region. The formation of the source/drain region includes forming a barrier region along a bottom surface and side surface of a recess in the active area. The barrier region includes arsenic having a first dopant concentration. The formation of the source/drain region further includes forming an epitaxial material on the barrier region in the recess. The epitaxial material includes phosphorous having a second dopant concentration.