公开(公告)号：US20140246710A1

公开(公告)日：2014-09-04

申请号：US13782112

申请日：2013-03-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun Hsiung TSAI ,  Sheng-Wen YU ,  Ying-Min CHOU ,  Yi-Fang PAI

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/0262 ,  H01L21/02639 ,  H01L29/66636

Abstract: A semiconductor substructure with an improved source/drain structure is described. The semiconductor substructure can include an upper surface; a gate structure formed over the substrate; a spacer formed along a sidewall of the gate structure; and a source/drain structure disposed adjacent the gate structure. The source/drain structure is disposed over or on a recess surface of a recess that extends below said upper surface. The source/drain structure includes a first epitaxial layer, having a first composition, over or on the interface surface, and a subsequent epitaxial layer, having a subsequent composition, over or on the first epitaxial layer. A dopant concentration of the subsequent composition is greater than a dopant concentration of the first composition, and a carbon concentration of the first composition ranges from 0 to 1.4 at.-%. Methods of making semiconductor substructures including improved source/drain structures are also described.

Abstract translation: 描述了具有改善的源极/漏极结构的半导体子结构。 半导体子结构可以包括上表面; 形成在所述基板上的栅极结构; 沿所述栅极结构的侧壁形成的间隔物; 以及邻近栅极结构设置的源极/漏极结构。 源极/漏极结构设置在在所述上表面下方延伸的凹部的凹部表面上或上。 源极/漏极结构包括在第一外延层之上或之上的第一外延层，其具有在界面表面之上或之上的第一组成，以及随后的外延层，具有随后的组成。 后续组合物的掺杂剂浓度大于第一组合物的掺杂剂浓度，并且第一组合物的碳浓度为0至1.4原子％。 还描述了制造包括改进的源极/漏极结构的半导体子结构的方法。

公开(公告)号：US20170352762A1

公开(公告)日：2017-12-07

申请号：US15226321

申请日：2016-08-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Yu YANG ,  Kai-Hsuan LEE ,  Sheng-Chen WANG ,  Sai-Hooi YEONG ,  Yi-Fang PAI ,  Yen-Ming CHEN

IPC: H01L29/78 ,  H01L29/45 ,  H01L29/08 ,  H01L29/06 ,  H01L29/04 ,  H01L29/66 ,  H01L21/311

CPC classification number: H01L29/7851 ,  H01L21/31111 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/7848 ,  H01L29/785

Abstract: A method of forming a semiconductor device includes forming a fin on a substrate and forming a source/drain region on the fin. The method further includes forming a doped metal silicide layer on the source/drain region and forming a super-saturated doped interface between the doped metal silicide and the source/drain region. An example benefit includes reduction of contact resistance between metal silicide layers and source/drain regions.

公开(公告)号：US20170110578A1

公开(公告)日：2017-04-20

申请号：US14883452

申请日：2015-10-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yasutoshi OKUNO ,  Cheng-Long CHEN ,  Meng-Chun CHANG ,  Sung-Li WANG ,  Yi-Fang PAI ,  Yusuke ONIKI

IPC: H01L29/78 ,  H01L29/161 ,  H01L21/768 ,  H01L29/165 ,  H01L29/04 ,  H01L23/535 ,  H01L29/66 ,  H01L29/24

CPC classification number: H01L29/7848 ,  H01L21/76805 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/535 ,  H01L29/045 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/665 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method of forming a semiconductor structure includes the following operations: (i) forming a fin structure on a substrate; (ii) epitaxially growing an epitaxy structure from the fin structure; (iii) forming a sacrificial structure surrounding the epitaxy structure; (iv) forming a dielectric layer covering the sacrificial structure; (v) forming an opening passing through the dielectric layer to partially expose the sacrificial structure; (vi) removing a portion of the sacrificial structure to expose a portion of the epitaxy structure; and (vii) forming a contact structure in contact with the exposed portion of the epitaxy structure. A semiconductor structure is disclosed herein as well.

公开(公告)号：US20190165100A1

公开(公告)日：2019-05-30

申请号：US15922643

申请日：2018-03-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-I KUO ,  Chii-Horng LI ,  Chia-Ling CHAN ,  Li-Li SU ,  Yi-Fang PAI ,  Wei Te CHIANG ,  Shao-Fu FU ,  Wei Hao LU

IPC: H01L29/08 ,  H01L29/167 ,  H01L29/36 ,  H01L21/223 ,  H01L21/02 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0847 ,  H01L21/02521 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/0262 ,  H01L21/2236 ,  H01L21/30604 ,  H01L21/3065 ,  H01L29/167 ,  H01L29/36 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7851

Abstract: The present disclosure relates generally to an epitaxy scheme for forming source/drain regions in a semiconductor device, such as an n-channel device. In an example, a method of manufacturing a semiconductor device includes forming an active area on a substrate. The active area includes a source/drain region. The formation of the source/drain region includes forming a barrier region along a bottom surface and side surface of a recess in the active area. The barrier region includes arsenic having a first dopant concentration. The formation of the source/drain region further includes forming an epitaxial material on the barrier region in the recess. The epitaxial material includes phosphorous having a second dopant concentration.

公开(公告)号：US20190164835A1

公开(公告)日：2019-05-30

申请号：US15821969

申请日：2017-11-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Hao LU ,  Yi-Fang PAI ,  Tuoh-Bin NG ,  Li-Li SU ,  Chii-Horng LI

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/04 ,  H01L29/08 ,  H01L29/167 ,  H01L29/45 ,  H01L23/535 ,  H01L21/02

CPC classification number: H01L21/823418 ,  H01L21/02532 ,  H01L21/02573 ,  H01L21/02609 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/535 ,  H01L27/0886 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/167 ,  H01L29/45 ,  H01L29/7848

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a first fin structure and a second fin structure over a substrate. The semiconductor device structure also includes a gate structure over the first and second fin structure. The semiconductor device structure further includes a source/drain structure over the first and second fin structure. The source/drain structure includes a first semiconductor layer over the first fin structure and a second semiconductor layer over the second fin structure. The source/drain structure also includes a third semiconductor layer covering the first and second semiconductor layers. The third semiconductor layer has a surface with [110] plane orientation.