公开(公告)号：US20230387057A1

公开(公告)日：2023-11-30

申请号：US18365362

申请日：2023-08-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Chih Chiou ,  Chen-Hua Yu ,  Shih Ting Lin ,  Szu-Wei Lu

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/29 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  H01L25/00 ,  H01L21/48

CPC classification number: H01L24/08 ,  H01L21/565 ,  H01L23/295 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49827 ,  H01L23/562 ,  H01L24/80 ,  H01L25/0655 ,  H01L25/50 ,  H01L21/486 ,  H01L2924/35121 ,  H01L2224/08225 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: In an embodiment, a device includes: an interposer; a first integrated circuit device bonded to the interposer with dielectric-to-dielectric bonds and with metal-to-metal bonds; a second integrated circuit device bonded to the interposer with dielectric-to-dielectric bonds and with metal-to-metal bonds; a buffer layer around the first integrated circuit device and the second integrated circuit device, the buffer layer including a stress reduction material having a first Young's modulus; and an encapsulant around the buffer layer, the first integrated circuit device, and the second integrated circuit device, the encapsulant including a molding material having a second Young's modulus, the first Young's modulus less than the second Young's modulus.

公开(公告)号：US11056436B2

公开(公告)日：2021-07-06

申请号：US15175696

申请日：2016-06-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih Ting Lin ,  Szu-Wei Lu ,  Jing-Cheng Lin ,  Chen-Hua Yu

IPC: H01L23/538 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/532

Abstract: A method of forming a package assembly includes forming a first dielectric layer over a carrier substrate; forming a conductive through-via over the first dielectric layer; treating the conductive through-via with a first chemical, thereby roughening surfaces of the conductive through-via; and molding a device die and the conductive through-via in a molding material.

公开(公告)号：US20240387198A1

公开(公告)日：2024-11-21

申请号：US18786739

申请日：2024-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih Ting Lin ,  Szu-Wei Lu ,  Kuo-Chiang Ting ,  Shang-Yun Hou ,  Chi-Hsi Wu ,  Weiming Chris Chen

IPC: H01L21/56 ,  H01L21/48 ,  H01L21/768 ,  H01L23/31 ,  H01L23/538

Abstract: A method includes attaching semiconductor devices to an interposer structure, attaching the interposer structure to a first carrier substrate, attaching integrated passive devices to the first carrier substrate, forming an encapsulant over the semiconductor devices and the integrated passive devices, debonding the first carrier substrate, attaching the encapsulant and the semiconductor devices to a second carrier substrate, forming a first redistribution structure on the encapsulant, the interposer structure, and the integrated passive devices, wherein the first redistribution structure contacts the interposer structure and the integrated passive devices, and forming external connectors on the first redistribution structure.

公开(公告)号：US20240379602A1

公开(公告)日：2024-11-14

申请号：US18781022

申请日：2024-07-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Chih Chiou ,  Chen-Hua Yu ,  Shih Ting Lin ,  Szu-Wei Lu

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/29 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065

Abstract: In an embodiment, a device includes: an interposer; a first integrated circuit device bonded to the interposer with dielectric-to-dielectric bonds and with metal-to-metal bonds; a second integrated circuit device bonded to the interposer with dielectric-to-dielectric bonds and with metal-to-metal bonds; a buffer layer around the first integrated circuit device and the second integrated circuit device, the buffer layer including a stress reduction material having a first Young's modulus; and an encapsulant around the buffer layer, the first integrated circuit device, and the second integrated circuit device, the encapsulant including a molding material having a second Young's modulus, the first Young's modulus less than the second Young's modulus.

公开(公告)号：US20220375890A1

公开(公告)日：2022-11-24

申请号：US17876159

申请日：2022-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Chih Chiou ,  Chen-Hua Yu ,  Shih Ting Lin ,  Szu-Wei Lu

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/29 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  H01L25/00 ,  H01L21/48

Abstract: In an embodiment, a device includes: an interposer; a first integrated circuit device bonded to the interposer with dielectric-to-dielectric bonds and with metal-to-metal bonds; a second integrated circuit device bonded to the interposer with dielectric-to-dielectric bonds and with metal-to-metal bonds; a buffer layer around the first integrated circuit device and the second integrated circuit device, the buffer layer including a stress reduction material having a first Young's modulus; and an encapsulant around the buffer layer, the first integrated circuit device, and the second integrated circuit device, the encapsulant including a molding material having a second Young's modulus, the first Young's modulus less than the second Young's modulus.

公开(公告)号：US20220068856A1

公开(公告)日：2022-03-03

申请号：US17139192

申请日：2020-12-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Chih Chiou ,  Chen-Hua Yu ,  Shih Ting Lin ,  Szu-Wei Lu

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/29 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  H01L25/00

Abstract: In an embodiment, a device includes: an interposer; a first integrated circuit device bonded to the interposer with dielectric-to-dielectric bonds and with metal-to-metal bonds; a second integrated circuit device bonded to the interposer with dielectric-to-dielectric bonds and with metal-to-metal bonds; a buffer layer around the first integrated circuit device and the second integrated circuit device, the buffer layer including a stress reduction material having a first Young's modulus; and an encapsulant around the buffer layer, the first integrated circuit device, and the second integrated circuit device, the encapsulant including a molding material having a second Young's modulus, the first Young's modulus less than the second Young's modulus.

公开(公告)号：US20180337137A1

公开(公告)日：2018-11-22

申请号：US16046399

申请日：2018-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih Ting Lin ,  Szu-Wei Lu ,  Jing-Cheng Lin ,  Chen-Hua Yu

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/532

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/53228 ,  H01L23/5384 ,  H01L23/5386 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/15311 ,  H01L2924/00014

Abstract: A method of forming a package assembly includes forming a first dielectric layer over a carrier substrate; forming a conductive through-via over the first dielectric layer; treating the conductive through-via with a first chemical, thereby roughening surfaces of the conductive through-via; and molding a device die and the conductive through-via in a molding material.

公开(公告)号：US11817410B2

公开(公告)日：2023-11-14

申请号：US17876159

申请日：2022-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Chih Chiou ,  Chen-Hua Yu ,  Shih Ting Lin ,  Szu-Wei Lu

IPC: H01L21/56 ,  H01L23/31 ,  H01L25/065 ,  H01L23/00 ,  H01L23/29 ,  H01L23/498 ,  H01L25/00 ,  H01L21/48

CPC classification number: H01L24/08 ,  H01L21/486 ,  H01L21/565 ,  H01L23/295 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49827 ,  H01L23/562 ,  H01L24/80 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/08225 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/35121

Abstract: In an embodiment, a device includes: an interposer; a first integrated circuit device bonded to the interposer with dielectric-to-dielectric bonds and with metal-to-metal bonds; a second integrated circuit device bonded to the interposer with dielectric-to-dielectric bonds and with metal-to-metal bonds; a buffer layer around the first integrated circuit device and the second integrated circuit device, the buffer layer including a stress reduction material having a first Young's modulus; and an encapsulant around the buffer layer, the first integrated circuit device, and the second integrated circuit device, the encapsulant including a molding material having a second Young's modulus, the first Young's modulus less than the second Young's modulus.

公开(公告)号：US20220359231A1

公开(公告)日：2022-11-10

申请号：US17815434

申请日：2022-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih Ting Lin ,  Szu-Wei Lu ,  Kuo-Chiang Ting ,  Shang-Yun Hou ,  Chi-Hsi Wu ,  Weiming Chris Chen

IPC: H01L21/56 ,  H01L21/768 ,  H01L21/48 ,  H01L23/538

Abstract: A method includes attaching semiconductor devices to an interposer structure, attaching the interposer structure to a first carrier substrate, attaching integrated passive devices to the first carrier substrate, forming an encapsulant over the semiconductor devices and the integrated passive devices, debonding the first carrier substrate, attaching the encapsulant and the semiconductor devices to a second carrier substrate, forming a first redistribution structure on the encapsulant, the interposer structure, and the integrated passive devices, wherein the first redistribution structure contacts the interposer structure and the integrated passive devices, and forming external connectors on the first redistribution structure.

公开(公告)号：US11469197B2

公开(公告)日：2022-10-11

申请号：US17139192

申请日：2020-12-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Chih Chiou ,  Chen-Hua Yu ,  Shih Ting Lin ,  Szu-Wei Lu

IPC: H01L21/56 ,  H01L23/31 ,  H01L25/065 ,  H01L23/00 ,  H01L23/29 ,  H01L23/498 ,  H01L25/00 ,  H01L21/48

Abstract: In an embodiment, a device includes: an interposer; a first integrated circuit device bonded to the interposer with dielectric-to-dielectric bonds and with metal-to-metal bonds; a second integrated circuit device bonded to the interposer with dielectric-to-dielectric bonds and with metal-to-metal bonds; a buffer layer around the first integrated circuit device and the second integrated circuit device, the buffer layer including a stress reduction material having a first Young's modulus; and an encapsulant around the buffer layer, the first integrated circuit device, and the second integrated circuit device, the encapsulant including a molding material having a second Young's modulus, the first Young's modulus less than the second Young's modulus.